|
A case study in networks-on-chip design for embedded video |
J. Xu, W. Wolf, J. Henkel, S. Chakradhar, T. Lv |
In Proceedings of Design Automation and Test in Europe Conference and Exhibition (DATE) |
|
6-20 Feb. 2004 |
Vol. 2, pp. 770 - 775 |
|
A Comparison of Network-on-Chip and Bussses |
Arteris |
|
Design and Reuse |
May 30 2005 |
http://www.us.design-reuse.com/articles/article10496.html |
|
A delay model for router micro-architectures |
L.S. Peh, W.J. Dally |
|
IEEE Micro |
Jan/Feb 2001 |
26-34 |
|
A delay model for router micro-architectures |
L.-S.Peh and W.J. Dally |
|
|
Jan/Feb.2001 |
IEEE Micro, pp.26-34 |
|
A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs |
F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini |
|
|
Mar. 2007 |
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3,pp. 421-434 |
|
A Network Traffic Generator Model for |
S. Mahadevan, M. Storgaard, R. Olsen, J. Sparsoe, J. Madsen, F. Angiolini, and L. Benini |
DATE 2005 |
|
2005 |
pp. 780-785 |
|
A statistical traffic model for on-chip interconnection networks |
V. Soteriou, H. Wang, L.-S. Peh |
|
MASCOTS |
2006 |
104-116 |
|
A Study on Communication Issues for Systems-on-Chip |
C. A. Zeferino, M. E. Kreutz, L. Carro, A. A. Susin |
15th Symposium on Integrated Circuits & Systems (SBCCI),2002 |
Proceedings, 15th SBCCI 2002 |
2002 |
121-126 |
|
An Energy and Performance Exploration of Network-on-Chip Architectures |
A. Banerjee, P.T. Wolkotte, R.D. Mullins, S.W. Moore, G.J.M. Smit |
|
|
March 2009 |
IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3, pp. 319-329 |
|
Analysis of error recovery schemes for networks on chip |
S. Murali, et al. |
|
IEEE Design and Test; Volume 25, Issue 5 |
2005 |
434-442 |
|
Analysis of Power Consumption on Switch Fabrics in Networks Routers |
T.T. Ye, L. Benini, G. de Michelli |
Design Automation Conference (DAC) 2002 |
Proceedings, DAC 2002 |
2002 |
524-529 |
|
Analyzing on-chip Communication in a MPSoC Environment |
M. Loghi, F. Angiolini, D Bertozzi, L. Benini, R. Zafalon |
Design, Automation and Test in Europe (DATE) 2004 |
Proceedings, DATE 2004 Volume: 2 |
February 16-20, 2004 |
752-757 |
|
Analyzing on-chip communication in a MPSoC environment |
M. Loghi, F.Angiolini, D. Bertozzi, L. Benini, and R. Zafalon |
DATE Feb.2004 |
|
|
pp. 752-757 |
|
Automated Bus Generation for Multiprocessor SoC Design |
K. Ryu, V. Mooney |
Design Automation and Test in Europe (DATE) 2003 |
Proceedings, DATE 2003 |
March 2003 |
282-287 |
|
Benchmarking mesh and hierarchical bus networks in system-on-chip context |
E. Salminen |
|
Journal of Systems Architectures; Volume 53, Issue 8 |
Aug. 2007 |
477-488 |
|
Benchmarking of On-Chip Interconnection Networks |
Daniel Wiklund, Sumant Sathe, and Dake Liu |
Proc of the International Conference on Microelectronics (ICM), Carthage, Tunisia |
|
Dec. 6-8, 2004 |
pp. 621 - 624 |
|
Communication architectures for system-on-chip |
M. Kreutz, et al. |
|
SBCCI |
2001 |
14-19 |
|
Comparative analysis of serial vs parallel links in noc |
A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar |
Int'l Symposium on Soc |
|
2004 |
185-188 |
|
Comparison of synthesized bus and crossbar interconnection architectures |
V. Lahtinen, et al. |
|
ISCAS; Vol 5 |
May 2003 |
433-436 |
|
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness |
F. Angiolini, P. Meloni, S. Carta, L. Benini, L. Raffo |
Design, Automation and Test in Europe (DATE) |
|
06-10 March 2006 |
Vol. 1, pp. 1- 6 |
|
Cost considerations in network on chip |
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny |
|
the VLSI Journal, Vol. 38, Iss. 1 |
Oct. 2004 |
19-42 |
|
Design space exploration and prototyping for on-chip multimedia applications |
H. G. Lee, et al. |
DAC |
|
Jul. 2006 |
137-142 |
|
Distributed Bus Arbitration Algorithm Comparison on FPGA Based MPEG-4 Multiprocessor SoC |
A. Kulmala, E. Salminen, T. Hamalainen |
|
IET Computers and Digital Techniques |
2008 |
|
|
Energy and latency evaluation of NoC topologies |
M. Kreutz, et al. |
|
ISCAS; Vol 6 |
May 2005 |
5866-5869 |
|
Error control schemes for on-chip communication links: the energy-reliability tradeoff |
D. Bertozzi, L.Benini,and G. de Micheli |
|
|
Jun. 2005 |
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.24, no. 6, pp.818-831 |
|
Evaluating application mapping using network simulation |
T. Salminen, J.-P. Soininen |
In International Symposium on System-on-Chip |
|
November 19-21 2003 |
pp.27-30 |
|
Evaluating NoC Communication Backbones with Simulation |
R. Thid, M. Millberg, A. Jantsch |
IEEE NorChip Conference |
Proceedings, IEEE NorChip Conference |
November 2003 |
27-30 |
|
Evaluating SoC Network Performance in MPEG-4 Encoder |
A. Kulmala, E. Salminen, M. Hannikainen, T. Hamalainen |
|
The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
May 2008 |
19 pages |
|
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application |
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen |
|
|
July 24 - 28, 2006 |
143 - 148. |
|
Evaluation of current QoS mechanisms in network-on-chip |
A. Mello, L. Tedesco, N. Calazans, F. Moraes |
Int'l Symposium on Soc |
|
Nov. 3006 |
115-118 |
|
Evaluation of on-chip networks using deflection routing |
Z. Lu, M. Zhong, A. Jantsch |
|
GLSVLSI |
May 2006 |
296-301 |
|
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures |
K. Lahiri, A. Raghunathan, S. Dey |
Conference on VLSI Design |
|
2001 |
29-35 |
|
Fault tolerance overhead in network-on-chip flow control |
Pullini, F. Angiolini, D. Bertozzi, L. Benini |
18th annual symposium on Integrated circuits and system design (SBCCI), Florianolpolis, France, 2005 |
|
2005 |
224 - 229 |
|
Flexible bus and NoC performance analysis with configurable synthetic workloads |
R. Thid, I. Sander, A. Jantsch |
|
DSD |
2006 |
681-688 |
|
Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance |
F. Dumitrascu, I. Bacivarov, L. Pieralisi, M. Bonaciu, A.A. Jerraya |
Design, Automation and Test in Europe (DATE) |
Vol. 2, 06-10 |
March 2006 |
1-6 |
|
Hierarchical Interconnects for On-chip Clustering |
A. Aggarwal, M. Franklin |
IPDPS 2002 |
Proceedings, IPDPS 2002, Abstracts and CD-ROM |
2002 |
602-609 |
|
High Level Estimation of the Area and Power Consumption of On-Chip Interconnects |
D. Langen, A. Brinkmann, U. Rckert |
13th Annual IEEE International ASIC/SOC Conference |
Proceedings, 13th Annual IEEE International ASIC/SOC Conf |
2000 |
297-301 |
|
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs |
Hui Zhang, M. Wan, G. Varghese, J. Rabaey |
IEEE Computer Society Annual Workshop on VLSI |
|
April 8-9, 1999 |
pp. 2-8 |
|
Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling |
R. Kumar, V. Zyuban, D.M.Tullsen |
International Symposium on Computer Architecture (ISCA) |
|
4-8 June 2005 |
408 - 419 |
|
Methodology for design, modeling, and analysis of networks-on-chip |
J. Xu, et al. |
|
ISCAS |
May 2005 |
1778-1781 |
|
Models for communication tradeoffs on systems-on-chip |
C.A. Zeferino, et al. |
|
IP based design |
Oct. 2002 |
394-400 |
|
Network-on-chip benchmarking specification Part 2: Microbenchmark Specification version 1.0 |
Z. Lu, A. Jantsch, E. Salminen, C. Grecu |
|
OCP-IP |
June 2008 |
16 pages |
|
Network-on-chip benchmarks specification Part 1: application modeling and hardware description |
E. Salminen, C. Grecu, T. Hamalainen, A. Ivanov |
|
OCP-IP |
April 2008 |
15 pages |
|
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. IEEE Trans. Computers 58(1) |
B. Feero, P.P. Pande |
|
|
2009 |
pp. 32-45 |
|
On Network-on-Chip Comparison |
E. Salminen, A. Kulmala, T. Hamalainen |
Euromicro Conference on Digital System Design |
|
August 27-31, 2007 |
503-510 |
|
Orion: a power-performance simulator for interconnection networks |
Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik |
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture |
|
November 18, 2002 |
294-305 |
|
Packetization and routing analysis of on-chip multiprocessor networks |
T.T. Ye, L. Benini, G. de Micheli |
|
Journal of Systems Architecture; Volume 50, Issues 2-3 |
February 2004 |
Pages 81-104 |
|
Performance Analysis of Systems with Multi-Channel Communication Architectures |
K. Lahiri, A. Raghunathan, S. Dey |
13th International Conference on VLSI Design |
Proceedings, 13th International Conference on VLSI Design |
January 2000 |
530-537 |
|
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures |
P.P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh |
IEEE Transactions on Computers |
Volume 54, Issue 8 |
Aug. 2005 |
pp. 1025 - 1040 |
|
Performance evaluation for three-dimensional networks-on-chip |
B. Feero, P. Pande |
|
ISVLSI |
2007 |
305-310 |
|
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures |
G. Palermo, C. Silvano |
|
Lecture Notes in Computer Science, Volume 3254 |
Jan 2004 |
521 - 531 |
|
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks |
V. Soteriou, et al. |
|
IEEE Trans. VLSI Syst. Vol 15, Issue 8 |
Aug. 2007 |
401-408 |
|
Polaris:Asystem-level roadmapping toolchain for on-chip interconnection networks |
V.Soteriou, N. Eisley, H. Wang, B.Li, and L.-S. Peh |
|
|
Aug.2007 |
IEEETrans. VLSI Syst., vol.15, no.8, pp.855-868 |
|
Power analysis of link level and end-to-end data protection in networks on chip |
A. Jantsch, R. Lauter, A. Vitkowski |
|
ISCAS; Volume 2 |
2005 |
1770-1773 |
|
Power analysis of system-level on-chip communication architectures |
Kanishka Lahiri, Anand Raghunathan |
Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), Stockholm, Sweden |
|
Sept. 8-10, 2004 |
pp. 236 - 241 |
|
Power Comparison of Throughput Optimized IC Busses |
E. Malley, A. Salinas, K. Ismail, L. Pileggi |
IEEE Computer Society Annual Symposium on VLSI, 2003 |
Proceedings. IEEE Computer Society Annual Symposium on VLSI |
February 20-21, 2003 |
35-44 |
|
QNoC: QoS architecture and design process for network on chip |
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, Edited by: A. Jantsch, J. Oberg and H. Tenhunen |
|
Journal of Systems Architecture, Volume 50, Issues 2-3, Special issue on networks on chip |
February 2004 |
105-128, Pages 61-168 |
|
Quality-of-service and error control techniques for mesh-based network-on-chip architectures |
P.Vellanki, N.Banerjee,and K.S.Chatha |
|
|
Jan.2005 |
Integration, the VLSI Journal,vol.38,no.3,pp.353-382 |
|
Reconfigurable fabric interconnects |
S. Vassiliadis, I. Sourdis |
|
Int'l Symposium on Soc |
Nov. 2006 |
41-44 |
|
Requirements for Network-on-Chip Benchmarking |
Erno Salminen, Tero Kangas, Timo D. Hmlinen, Jouni Riihimki |
|
Norchip, Oulu, Finland, November 21-22, 2005 |
2005 |
pp. 82-85 |
|
SPIN: a Scalable, Packet Switched, on-chip Micro-network |
A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C.A. Zeferino |
Design, Automation and Test in Europe (DATE) 2003 |
Proceedings, DATE 2003 |
2003 |
70-73 |
|
System-level point-to-point communication synthesis using floorplanning information |
J. Hu, Y. Deng, R. Marculescu |
|
ASP-DAC/VLSI |
Jan. 2002 |
573-579 |
|
T.Bartic, J.-Y.Mignolet,V.Nollet,T.Marescaux,D.Verkest,S.Vernalde, and R. Lauwereins |
Topology adaptive network-on-chip design and implementation |
|
|
Jul. 2005 |
IEEE Proc. Comput. Digit. Tech., vol. 152, no. 4, pp. 467-472 |
|
The impact of communication on the scalability of the data-parallel video encoder on MPSoC |
E. Salminen, T. Kangas, T. Hamalainen |
Int'l Symposium on Soc |
|
Nov. 2006 |
191-194 |
|
The impact of higher communication layers on NoC supported MP-SoCs |
T. Marescaux, E. Brockmeyer, and H.Corporaal |
NOCS, May 2007 |
|
|
pp. 107-116 |
|
The Power Analysis of Interconnect Structures |
Yan Zhang, Wu Ye, R.M. Owens, M.J. Irwin |
10th Annual IEEE International ASIC Conference, 1997 |
Proceedings, 10th Annual IEEE International ASIC Conf., 1997 |
1997 |
25-29 |
|
Topology adaptive network-on-chip design and implementation |
T. Bartic |
|
IEE Proc. Comput. Digit. Tech; Vol 152, Issue 4 |
Jul. 2005 |
467-472 |
|
Trade-offs in the configuration of a network on chip for multiple use-cases |
A. Hansson and K. Goossens |
NOCS, May 2007 |
|
2007 |
pp.233-242 |
|
Traffic configuration for evaluating networks on chips |
Zhonghai Lu, A. Jantsch |
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC) |
|
20-24 July 2005 |
pp. 535 - 540 |
|
Using VCI in a on-chip system |
Charlery Herv, Greiner Alain, Encrenaz Emmanuelle, Mortiez Laurent, Andriahantenaina Adrijean |
Proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin, Poland |
|
June 2004 |
pp. 571-576 |
