|
A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling |
R. Bashirullah, Wentai Liu, R. Cavin, D. Edwards |
|
Digest of Technical Papers Symposium on VLSI Circuits |
17-19 June 2004 |
pp. 392 - 393 |
|
A 600-MHz Single-Chip Multiprocessor with 4.8-GB/s Internal Shared Pipelined Bus and 512-kB Internal |
S. Kaneko, H. Kondo, N. Masui, K. Ishimi, T. Itou, M. Satou, N. Okumura, Y. Takata, H. Takata, M. Sakugawa, T. Higuchi, S. Ohtani, K. Sakamoto, N. Ishikawa, M. Nakajima, S. Iwata, K. Hayase, S. Nakano, S. Nakazawa, K. Yamada, T. Shimizu |
|
IEEE Journal of Solid-State Circuits; |
January 2004 |
184-193 |
|
A dual round-robin arbiter for split-transaction buses in system-on-chip implementations |
J. Reed, N. Manjikian |
Canadian Conference on Electrical and Computer Engineering; Volume 2 |
|
May 2004 |
pp. 835 - 840 |
|
A high performance bus communication architecture through bus splitting |
Ruibing Lu, Cheng-Kok Koh |
|
Proceedings of the Asia and South Pacific Design Automation |
27-30 Jan. 2004 |
pp. 751 - 755 |
|
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks |
T. Richardson, et al. |
|
VLSI Design |
Jan. 2006 |
|
|
A Single-Chip, 1.6-Billion, 16-b MAC/s Multiprocessor DSP |
B. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C. J. Nicol, J. H. O'Neill, J. Othmer, E. Sckinger, K. J. Singh, J. Sweet, C. J. Terman, and J. Williams |
|
IEEE Journal of Solid-State Circuits, Volume: 35, Issue: 3 |
March 2000 |
412-424 |
|
A2B Synchronous System Bus and A2R Register/Peripheral Bus in an ARC Based Multiprocessor System-on- |
Advanced Architectures |
|
Application Note: AN003 |
2001 |
|
|
AHB-Lite overview |
ARM Ltd. |
|
ARM SDVI 0044A |
2001 |
|
|
AMBA AXI Protocol Revision:r0p0 Specification |
ARM Ltd. |
2003 Altera |
Avalon Bus Sepcification Reference Manual 2.3 |
July 2003 |
106 pages |
|
AMBA: Enabling Reusable On-Chip Designs |
D. Flynn |
IEEE Micro |
Volume: 17, Issue 4 |
July-August 1997 |
20-27 |
|
An Alternative Architecture for on-chip Global Interconnect: Segmented Bus Power Modeling |
Yan Zhang, Wu Ye, M.J. Irwin |
32nd Asilomar Conference on Signals, Systems & Computers, 19 |
Conference Record, 32nd Asilomar Conference on Signals Syste |
1998 |
1062-1065 |
|
An Efficient Bus Architecture for System-on-chip Design |
B. Cordan |
IEEE CICC 1999 |
Proceedings, IEEE CICC 1999 |
May 16-19, 1999 |
623- 626 |
|
Arbitration for the segmented bus architecture |
T. Seceleanu, S. Stancescu |
Proceedings of Internatioanl Semiconductor Conference (CAS) |
|
4-6 Oct. 2004 |
pp. 487 - 490 |
|
ARM7100-a High-Integration, Low-power Microcontroller for PDA applications |
G. Budd, G. Milne |
Compcon 1996 |
Technologies for the Information Superhighway Digest |
1996 |
182-187 |
|
Asynchronous Macrocell Interconnect Using MARBLE |
W.J. Bainbridge, S.B. Furber |
4th International Symposium on Advanced Research in Asynchronous Circuits and Systems |
Proceedings, 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems |
March 30-April 2, 1998 |
122-132 |
|
Bus Architecture of a System on a Chip with User-Configurable System Logic |
S. Winegarden |
|
IEEE Journal of Solid-State Circuits, Volume: 35, Issue: 3 |
March 2000 |
425- 433 |
|
Bus Structures as the Basic Building Blocks of Network-on-Chip |
V. Lahtinen, E. Salminen, K. Kuusilinna, T. Hmlinen; Eds. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch |
|
Interconnect-Centric Design for Advanced SoC and NoC; Kluwer |
2004 |
207-230 |
|
Buses |
W.W. Hsu, Jih-Kwon Peir, A.B. Tucker, Jr. (Editor-in-Chief) |
|
The Computer Science and Engineering Handbook, CRC Press in |
1997 |
40 pages |
|
Design of AMBA wrappers for multiple-clock operations |
Nam-Joon Kim, Hyuk-Jae Lee |
International Conference on Communications, Circuits and Systems (ICCCAS) |
|
27-29 June 2004 |
Vol.2, pp. 1438 - 1442 |
|
Efficient exploration of on-chip bus architectures and memory allocation |
Sungchan Kim, Chaeseok Im, Soonhoi Ha |
Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), Stockholm, Sweden |
|
8-10 Sept. 2004 |
pp. 248 - 253 |
|
Efficient Modeling and Synthesis of On-Chip Communication Protocols for Network-on-Chip Design |
Robert Siegmund and Dietmar Muller |
International Symposium on Circuits and Systems (ISCAS) 2003 |
|
2003 |
|
|
Fast Exploration of Bus-based On-chip Communication |
S. Pasricha, N. Dutt, M. Ben-Romdhane |
Proceedings of international conference on Hardware/software codesign and system synthesis (CODES) |
|
8-10 September 2004 |
pp 242 - 247 |
|
FLEXBUS: A High Performance System-on-Chip Communication Architecture with a Dynamically Configurabl |
K. Sekar, K. Lahiri, A. Raghunathan, S. Dey |
Design Automation Conference (DAC) |
Proc. Design Automation Conference |
June 2005 |
571 - 574 |
|
HIBI Communication Network for System-on-Chip |
E. Salminen, T. Kangas, J. Riihimaki, V. Lahtinen, K. Kuusilinna, T. Hamalainen |
|
Journal of VLSI Signal Processing-Systems for Signal, Image and Video Technology; Volume 43, Issue 2-3 |
June 2006 |
185-205 |
|
HIBI v.2 Interconnection Network for System-on-Chip |
E. Salminen, V. Lahtinen, T. Kangas, J. Riihimki, K. Kuusilinna, T.D. Hmlinen |
|
LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS) |
2004 |
412-422 |
|
Integration Architecture for System-on-a-chip Design |
D. Wingard, A. Kurosawa |
IEEE Custom Integrated Circuits Conference (CICC) 1998 |
Proceedings, IEEE CICC1998 |
May 11-14, 1998 |
85-88 |
|
Interconnection Scheme for Continuous-media Systems-on-a-chip |
V. Lahtinen, K. Kuusilinna, T. Kangas, T. Hmlinen |
|
Microprocessors and Microsystems, Volume: 26, Issue 3 |
April 2002 |
123-138 |
|
LOTTERYBUS: A New HighPerformance Communication Architecture for System-on-Chip Designs |
K. Lahiri, A. Raghunathan, G. Lakshminarayana |
Design Automation Conference (DAC) 2001 |
Proceedings, DAC 2001 |
2001 |
15-20 |
|
Low-Latency Interconnection For IP-Block Based Multimedia Chips |
K. Kuusilinna, T. Hamalainen, P. Liimatainen, J. Saarinen |
IASTED International Conference Parallel and Distributed Com |
|
December 14-16, 1998 |
411-416 |
|
MARBLE: an Asynchronous on-chip Macrocell Bus |
W.J. Bainbridge, S.B. Furber |
|
Microprocessors and Microsystems 24 |
2000 |
213-222 |
|
MicroNetwork-based Integration for SoCs |
D. Wingard |
Design Automation Conference (DAC) 2001 |
Proceedings, DAC 2001 |
2001 |
673-677 |
|
Multi-core SoC Platfrom Integration Using AMBA |
R.L. Veal, L. Petrosian, N. Stollon |
DesignCon 2002 |
|
2002 |
|
|
Multi-layer AHB Overview |
ARM Ltd. |
|
ARM DVI 0045A |
2001 |
|
|
NECoBus: a High-end SOC Bus with a Portable and Low-latency Wrapper-based Interface Mechanism |
K. Anjo, A. Okamura, T. Kajiwara, N. Mizushima, M. Omori, Y. Kuroda |
IEEE CICC 2002 |
Proceedings, IEEE CICC 2002 |
May 12-15, 2002 |
315- 318 |
|
Next Generation CoreConnect/spl Trade/ Processor Local Bus Architecture |
Hofmann, R., Drerup, B |
15th Annual IEEE International ASIC/SOC Conference, 2002 |
|
September 25-28, 2002 |
221- 225 |
|
Open Microprocessors Systems Initiative, PI-Bus VHDL Toolkit Version 3.1 |
M. Bassett, P. Lister, University of Sussex |
|
Open Micro-processor Systems Initiative (OMI) Concertation M |
November 8-9, 1994 |
|
|
Performance analysis of different arbitration algorithms of the AMBA AHB bus |
M. Conti, M. Caldari, G.B. Vece, S. Orcioni, C. Turchetti |
Design Automation Conference (DAC) |
|
June 7-11, 2004 |
pp. 618 - 621 |
|
Pipelined Bidirectional Bus Architecture for Embedded Multimedia |
Gang-Hoon Seo, Won-Yong Jung, Seongsoo Lee, Jae-Kyung Wee, |
|
Lecture Notes in Computer Science, Volume 3824, |
Nov 2005 |
Pages 350 - 359 |
|
Prefetching for Improved Bus Wrapper Performance in Cores |
R. Lysecky, F. Vahid |
|
ACM Transactions on Design Automation of Electronic Systems |
January 2002 |
|
|
Reconfigurable Memory Bus Systems using Multi-Gbps/pin CDMA I/O Transceivers |
Jongsun Kim, Zhiwei Xu, Frank Chang |
ISCAS 2003 |
Proceedings, ISCAS 2003 Volume: 2 |
2003 |
II-33- II-36 |
|
Samba-bus: a High Performance Bus Architecture for System-on-chips |
Ruibing Lu; Cheng-Kok Koh |
International Conference on Computer Aided Design (ICCAD) |
|
November 9-13, 2003 |
8-12 |
|
Self-timed ring architecture for SOC applications |
P. Liljeberg, J. Plosila, J. Isoaho |
IEEE International SOC [Systems-on-Chip] Conference |
|
September 2003 |
pp. 359- 362 |
|
SNP: a new communication protocol for SoC |
Jaesung Lee, Hyuk-Jae Lee, Chanho Lee |
International Conference on Communications, Circuits and Sys |
|
27-29 June 2004 |
Vol. 2, pp. 1419 - 1423 |
|
Specification for the: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Co |
|
|
Revision: B.3 |
September 7, 2002 |
|
|
Standard Bus vs. Bus Wrapper: Comparisons and Proposition of a Mixed Approach |
M. Bertola, G. Bois, G. Cyr |
2002 International Workshop on System-on-Chip for Real-Time |
|
July 2002 |
|
|
System Level Power Modeling and Simulation of High-end Industrial Network-on-Chip |
A. Bona, V. Zaccaria, R. Zafalon |
Design Automation and Test in Europe (DATE) 2004 |
Proceedings, DATE 2004; |
February 16-20, 2004 |
318-323 |
|
The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip |
W.J. Bainbridge, L.A. Plana, S.B. Furber |
Design Automation and Test in Europe (DATE) 2004 |
Proceedings, DATE 2004; Volume 3 |
February 16-20, 2004 |
274-279 |
|
Viper: A Multiprocessor SOC for Advanced Set-top Box and Digital TV Systems |
S. Dutta, R. Jensen, A. Rieckmann |
|
IEEE Design & Test of Computers, Volume: 18, Issue: 5 |
September-October 2001 |
21-31 |
|
White paper: CoreConnect Bus Architecture |
IBM Corporation |
|
|
1999 |
|
|
Wrapper-based Bus Implementation Techniques for Performance Improvement and Cost Reduction |
K. Anjo, A. Okamura, M. Motomura |
|
IEEE Journal of Solid-State Circuits; |
May 2004 |
804-817 |