| CoreCreator |
Core Configuration, Verification and Packaging. OCP 1.0 compliant. |
OCP International Partnership |
OCP-IP Administration |
503-619-0560
admin@ocpip.org |
| CoWare Model Designer |
CoWare Model Designer speeds the concurrent design of SoCs with embedded software at the electronic system level. CoWare Model Designer is a native IEEE 1666 SystemC toolset, providing simulation and debug capabilities for transaction-level modeling. It comes standard with the SystemC Modeling Library (or SCML, based on a foundation of OSCI and OCP-IP standards), user guidelines for modeling reusable transaction level peripherals, and generic IP examples that make learning TLM easier. Together with the CoWare Model Library, the largest IP model library for SystemC, users can rapidly create and validate SoC designs at the transaction level in SystemC. |
CoWare, Inc. |
Patrick Sheridan |
408-392-8528
psheridan@coware.com |
| CoWare Platform Architect |
CoWare Platform Architect speeds the concurrent design of SoCs with embedded software at the electronic system level. CoWare Platform Architect combines hardware/software partitioning and platform assembly together with simulation, debug and analysis capabilities. CoWare Platform Architect provides native IEEE 1666 SystemC support, and comes standard with the SystemC Modeling Library (or SCML, based on a foundation of OSCI and OCP-IP standards), user guidelines for modeling reusable transaction level peripherals, and generic IP examples that make learning TLM easier. Together with the CoWare Model Library, the largest IP model library for SystemC, users can rapidly create and validate SoC designs at the transaction level in SystemC. |
CoWare, Inc. |
Patrick Sheridan |
408-392-8528
psheridan@coware.com |
| imPROVE-HDL |
An assertion-based formal verification tool that can be used on a wide range of design blocks. imPROVE-HDL includes a GUI, xshell and script mode which make it very easy to use. The tool can seamlessly fit in a simulation-based verification flow or in a Specman Elite. |
AerieLogic |
Samuel Dellacherie |
+33 (0)2 31 53 30 05
samuel.dellacherie@aerielogic.com |
| imPROVE-HPK |
A formal verification tool dedicated to the automatic verification of hardware designs based on standard protocol interfaces (such as OCP, AmbaAHB, PCI, PCI-X, etc). imPROVE-HPK automatically creates the complete protocol environment of the design and then automatically checks that the protocol properties (including functional performance analysis properties) and coverage scenarios are met. |
AerieLogic |
Samuel Dellacherie |
+33 (0)2 31 53 30 05
samuel.dellacherie@aerielogic.com |
| iSolve OCP Transactor |
iSolve OCP transactor is part of Veloce transaction-based acceleration solutions enabling hardware assisted verification of OCP based designs. |
Mentor Graphics |
Kenneth Larsen |
kenneth_larsen@mentor.com |
| OCP Assertion Based Verification IP |
Cadence® Incisive® Assertion-Based Verification IP (ABVIP) for OCP 2.0, 2.1 and 2.2 works together with Cadence's formal and/or dynamic verification engines to increase quality and productivity and provides a predictable path to verification closure. When used together with Incisive Formal Verifier (IFV) the Incisive ABVIP enables design engineers to immediately verify protocol functionality and compliance since no testbench is needed nor must any stimuli be created. |
Cadence Design Systems, Inc. |
Pete Heller |
408-914-6896
peteh@cadence.com |
| OCP Hardware Protocol Kit |
The OCP Hardware Protocol Kit has been designed to enable quick and exhaustive verification of any OCP compliant hardware block. The kit automatically creates the complete OCP protocol environment of the design and then automatically checks that the OCP protocol properties (including functional performance analysis properties) and OCP coverage scenarios are met. The OCP HPK covers both the 2.0 and 1.0 versions of the OCP. |
AerieLogic |
Samuel Dellacherie |
+33 (0)2 31 53 30 05
samuel.dellacherie@aerielogic.com |
| OCP UVC 2.2 |
The Cadence® Incisive® Verification IP (VIP) family for Open Core Protocols (OCP) provides broad verification engine support together with the most automated protocol compliance verification solution available. The Incisive VIP OCP UVC is available for all OCP versions and supports all common topologies. And since Incisive VIP for OCP complies with the Open Verification Methodology (OVM), it supports multiple languages including SystemVerilog, e, Verilog®, and VHDL. |
Cadence Design Systems |
Pete Heller |
408-914-6896
peteh@cadence.com |
| Questa Multi-View Verification Component (MVC) for OCP |
OCP MVC is part of Questa MVC library, a complete SystemVerilog library solution for OVM based verification environments with stimulus generation, reference checking and functional coverage enabling fast development of tests for all aspects of the OCP protocol for directed and constrained-random verification environments. |
Mentor Graphics |
Kenneth Larsen |
kenneth_larsen@mentor.com |
| Questa SystemVerilog Assertion Monitor for OCP |
OCP assertion monitor is part of Questa Verification Library, a complete SystemVerilog library solution for assertion-based verification (ABV) with assertion checkers and protocol monitors, enabling fast adoption and deployment of ABV with simulation, emulation and formal verification. |
Mentor Graphics |
Kenneth Larsen |
kenneth_larsen@mentor.com |
| Sonics OCP Library for Verification (SOLV) |
Debugging, performance tuning and validation of complex intellectual property (IP) cores using OCP interfaces. |
Sonics, Inc. |
Stephen Tomasello |
408-474-2800
stephen@sonicsinc.com |
| SonicsStudio |
Architectural Exploration and SoC Integration Development Environment. |
Sonics, Inc. |
Stephen Tomasello |
408-474-2800
stephen@sonicsinc.com |
| SystemC OCP Transactional Models |
SystemC OCP models for Transaction Layer 1 (TL1) and Transaction Layer 2 (TL2). |
OCP International Partnership |
OCP-IP Administration |
503-619-0560
admin@ocpip.org |
| DesignWare OCP 2.1 Verification IP |
Synopsys DesignWare� Verification IP for OCP provides a quick and efficient way to functionally verify OCP 2.1 interfaces. It enables the verification of master and slave devices in OCP systems and cores and provides 100% functional coverage as defined in section 4 of the OCPIP 2.0/2.1 Compliance Checks document.
The DesignWare VIP for OCP supports the Verification Methodology Manual for SystemVerilog. It also supports Verilog and VHDL testbenches. |
Synopsys Inc |
Neill Mullinger |
503 547 6048
neill.mullinger@synopsys.com or admin@ocpip.org |
| OCP-Conductor |
OCP Conductor - is a comprehensive transaction level graphical viewer for the OCP Socket. Transactions are visually extracted from simulations and presented in a user friendly and intuitive way. Higher level statistics are easy extracted and viewed. |
Duolog |
Brian Clinton |
+353-1-2178400
brian.clinton@duolog.com |
| OCP-Tracker |
OCP Tracker - is a graphical performance analysis engine for OCP-based SoC infrastructures. 3D and 2D visualization of performance related data is one of the keys to understanding how the system can cope with different types of traffic, enabling the identification and understanding of weaknesses in the architectural structure of a SoC. |
Duolog |
Brian Clinton |
+242-1-2178400
brian.clinton@duolog.com |
| Magillem |
The Eclipse based Magillem Core is at the heart of a fully featured flow optimization suite comprised of an IP-XACT packager, a platform assembly tool,a complete development environment, a flow control tool and a register view kit.
The Magillem suite is a one-of-a-kind innovative software tree, enabling flawless and homogeneous design flow integration for various targets such as ASICs, FPGAs, electronic boards, AMS domain and complex systems. Adaptation kits have been developed for each target.
Add-ons are also available to meet specific requirements of customers such as Reporting and Documentation, Safety and Traceability of Critical systems
Designs.
Key customers applications: specifications, virtual prototyping, verification, validation, legacy integration, management of obsolescence, etc. benefit from a
common backbone and seamless encapsulation into one unified environment.
MAGILLEM undisputed advantage lies in the extended potential given to users in programming their flow control, effectively integrating various
interoperable point tools and developing additional modules for missing functionalities. Flexibility and versatility are provided by the powerful Custom Generators Factory. |
Magillem Design Services |
Geday |
+33.1.40.21.35.50
geday@magillem.com |
| SOC-VSP |
Carbon's SOC-VSP software is the first virtual system prototyping solution that combines the power of ARM RealView SoC Designer simulation with Carbons ability to incorporate a designs RTL. Finally, a hardware-accurate, soft-model of a SoC that can be rapidly assembled and functionally validated on an engineers desktop months before silicon. ARM RealView SoC Designer enables System Architects to profile a SoC with end-to-end cycle accuracy including processors, busses, and peripheral models. Now with SOC-VSP software, Verilog and VHDL hardware designs can be added to the list.
Software Developers get an early jump on debugging their firmware with an integrated debugger and a hardware-accurate modelrather than waiting months for silicon or an idealized behavioral model to be developed. Hardware Designers can leverage fast mixed-level simulation, an integrated debugger, and a library of plug-in bus protocols to validate their complete system. ARM RealView SoC Designer and SOC-VSP software enable continuous validation of software and hardware from concept through volume production.
more: http://www.carbondesignsystems.com/corpsite/products/html/soc-vsp-product-brief.html |
Carbon Design Systems |
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| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
