| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you
can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
| Socrates-Weaver |
Socrates Weaver enables rapid IP Integration and Chip Assembly. IP reuse and efficient IP integration are essential for successful SoC development. Weaver is a revolutionary tool for IP integration that is the fastest and most efficient way to build and maintain complex systems. The unique rules-based integration methodology employed by Weaver maximizes the potential for IP, subsystem and system reuse. |
Duolog |
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| Magillem |
The Eclipse based Magillem Core is at the heart of a fully featured flow optimization suite comprised of an IP-XACT packager, a platform assembly tool,a complete development environment, a flow control tool and a register view kit.
The Magillem suite is a one-of-a-kind innovative software tree, enabling flawless and homogeneous design flow integration for various targets such as ASICs, FPGAs, electronic boards, AMS domain and complex systems. Adaptation kits have been developed for each target.
Add-ons are also available to meet specific requirements of customers such as Reporting and Documentation, Safety and Traceability of Critical systems
Designs.
Key customers applications: specifications, virtual prototyping, verification, validation, legacy integration, management of obsolescence, etc. benefit from a
common backbone and seamless encapsulation into one unified environment.
MAGILLEM undisputed advantage lies in the extended potential given to users in programming their flow control, effectively integrating various
interoperable point tools and developing additional modules for missing functionalities. Flexibility and versatility are provided by the powerful Custom Generators Factory. |
Magillem Design Services |
Geday |
+33.1.40.21.35.50
geday@magillem.com |
| SOC-VSP |
Carbon's SOC-VSP software is the first virtual system prototyping solution that combines the power of ARM RealView SoC Designer simulation with Carbons ability to incorporate a designs RTL. Finally, a hardware-accurate, soft-model of a SoC that can be rapidly assembled and functionally validated on an engineers desktop months before silicon. ARM RealView SoC Designer enables System Architects to profile a SoC with end-to-end cycle accuracy including processors, busses, and peripheral models. Now with SOC-VSP software, Verilog and VHDL hardware designs can be added to the list.
Software Developers get an early jump on debugging their firmware with an integrated debugger and a hardware-accurate modelrather than waiting months for silicon or an idealized behavioral model to be developed. Hardware Designers can leverage fast mixed-level simulation, an integrated debugger, and a library of plug-in bus protocols to validate their complete system. ARM RealView SoC Designer and SOC-VSP software enable continuous validation of software and hardware from concept through volume production.
more: http://www.carbondesignsystems.com/corpsite/products/html/soc-vsp-product-brief.html |
Carbon Design Systems |
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| Socrates-Spinner |
Socrates Spinner eases I/O Fabric Management. Modern SoC devices typically support multiple static and dynamic operating modes. This can result in thousands of top-level signals that need to be mapped to hundreds of I/O pins according to the target application. Spinner manages this increasingly complex area by specifying and auto-generating all of the logic associated with the chip I/O layer. |
Duolog |
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| Socrates-Bitwise |
Socrates Bitwise is your complete solution for Register and Memory Management. Effective HW/SW integration is one of the biggest challenges facing System-on-Chip (SoC) development teams. Registers and memory-maps are at the heart of the HW/SW interface. Bitwise manages the entire register and memory-map infrastructure for an IP or system, improving inter-team communications, enhancing design quality and greatly reducing workload. |
Duolog |
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| StudioXE |
Sonics’ StudioXE is a next-generation, modular, system-level design tool which enables the rapid integration and configuration of Sonics on-chip network IP for complex SoCs. StudioXE contains a variety of modules and components which allow designers to easily incorporate Sonics innovative on-chip communications IP into their SoC design flows. By compartmentalizing StudioXE’s functionality, Sonics has created a tool that enables small, fabless semiconductor companies as well as top tier semiconductor manufacturers to access and assimilate Sonics silicon proven technology across their SoC portfolio. |
Sonics, Inc. |
Stephen Tomasello |
408-457-2800
stephen@sonicsinc.com |
| OCP Conductor |
OCP Conductor is an innovative, detailed OCP transaction viewer that enables fine-grained analysis of bus transactions. A complete transaction sequence can be traced from request to response along with a host of related information about the transaction, permitting instant, powerful, high-level OCP transaction analysis and debug. Transactions are visually extracted from simulations and presented in a user friendly and intuitive way. |
Duolog |
Brian Clinton |
+353-1-2178400
brian.clinton@duolog.com |
| OCP Tracker |
OCP Tracker allows designers of OCP-based systems to tune their architectures to maximize performance. It provides graphical performance, statistical and transaction analysis of OCP interfaces and fabrics. It also enables validation of performance metrics via a built-in regression manager and seamlessly interfaces with OCP-IP’s CoreCreator II trace files to allow bandwidth, latency and other types of performance metrics to be analyzed. OCP Tracker’s 3D 360° navigation engine allows these metrics to be visualized in an intuitive way. It provides an understanding of how OCP systems cope with different types of traffic patterns thus enabling the identification of the optimal architectural structure of a SoC. |
Duolog |
Brian Clinton |
+242-1-2178400
brian.clinton@duolog.com |
| DesignWare OCP 2.1 Verification IP |
Synopsys DesignWare� Verification IP for OCP provides a quick and efficient way to functionally verify OCP 2.1 interfaces. It enables the verification of master and slave devices in OCP systems and cores and provides 100% functional coverage as defined in section 4 of the OCPIP 2.0/2.1 Compliance Checks document.
The DesignWare VIP for OCP supports the Verification Methodology Manual for SystemVerilog. It also supports Verilog and VHDL testbenches. |
Synopsys Inc |
Neill Mullinger |
503 547 6048
neill.mullinger@synopsys.com or admin@ocpip.org |
| SystemC OCP Transactional Models |
SystemC OCP models for Transaction Layer 1 (TL1) and Transaction Layer 2 (TL2). |
OCP International Partnership |
OCP-IP Administration |
503-619-0560
admin@ocpip.org |
| CoreCreator |
Core Configuration, Verification and Packaging. OCP 1.0 compliant. |
OCP International Partnership |
OCP-IP Administration |
503-619-0560
admin@ocpip.org |
| OCP Assertion Based Verification IP |
Cadence® Incisive® Assertion-Based Verification IP (ABVIP) for OCP 2.0, 2.1 and 2.2 works together with Cadence's formal and/or dynamic verification engines to increase quality and productivity and provides a predictable path to verification closure. When used together with Incisive Formal Verifier (IFV) the Incisive ABVIP enables design engineers to immediately verify protocol functionality and compliance since no testbench is needed nor must any stimuli be created. |
Cadence Design Systems, Inc. |
Pete Heller |
408-914-6896
peteh@cadence.com |
| OCP UVC 2.2 |
The Cadence® Incisive® Verification IP (VIP) family for Open Core Protocols (OCP) provides broad verification engine support together with the most automated protocol compliance verification solution available. The Incisive VIP OCP UVC is available for all OCP versions and supports all common topologies. And since Incisive VIP for OCP complies with the Open Verification Methodology (OVM), it supports multiple languages including SystemVerilog, e, Verilog®, and VHDL. |
Cadence Design Systems |
Pete Heller |
408-914-6896
peteh@cadence.com |
| Sonics OCP Library for Verification (SOLV) |
Debugging, performance tuning and validation of complex intellectual property (IP) cores using OCP interfaces. |
Sonics, Inc. |
Stephen Tomasello |
408-474-2800
stephen@sonicsinc.com |
| SonicsStudio |
Architectural Exploration and SoC Integration Development Environment. |
Sonics, Inc. |
Stephen Tomasello |
408-474-2800
stephen@sonicsinc.com |
| CoWare Platform Architect |
CoWare Platform Architect speeds the concurrent design of SoCs with embedded software at the electronic system level. CoWare Platform Architect combines hardware/software partitioning and platform assembly together with simulation, debug and analysis capabilities. CoWare Platform Architect provides native IEEE 1666 SystemC support, and comes standard with the SystemC Modeling Library (or SCML, based on a foundation of OSCI and OCP-IP standards), user guidelines for modeling reusable transaction level peripherals, and generic IP examples that make learning TLM easier. Together with the CoWare Model Library, the largest IP model library for SystemC, users can rapidly create and validate SoC designs at the transaction level in SystemC. |
CoWare, Inc. |
Patrick Sheridan |
408-392-8528
psheridan@coware.com |
| CoWare Model Designer |
CoWare Model Designer speeds the concurrent design of SoCs with embedded software at the electronic system level. CoWare Model Designer is a native IEEE 1666 SystemC toolset, providing simulation and debug capabilities for transaction-level modeling. It comes standard with the SystemC Modeling Library (or SCML, based on a foundation of OSCI and OCP-IP standards), user guidelines for modeling reusable transaction level peripherals, and generic IP examples that make learning TLM easier. Together with the CoWare Model Library, the largest IP model library for SystemC, users can rapidly create and validate SoC designs at the transaction level in SystemC. |
CoWare, Inc. |
Patrick Sheridan |
408-392-8528
psheridan@coware.com |
