| SOC-VSP |
Carbon's SOC-VSP software is the first virtual system prototyping solution that combines the power of ARM RealView SoC Designer simulation with Carbons ability to incorporate a designs RTL. Finally, a hardware-accurate, soft-model of a SoC that can be rapidly assembled and functionally validated on an engineers desktop months before silicon. ARM RealView SoC Designer enables System Architects to profile a SoC with end-to-end cycle accuracy including processors, busses, and peripheral models. Now with SOC-VSP software, Verilog and VHDL hardware designs can be added to the list.
Software Developers get an early jump on debugging their firmware with an integrated debugger and a hardware-accurate modelrather than waiting months for silicon or an idealized behavioral model to be developed. Hardware Designers can leverage fast mixed-level simulation, an integrated debugger, and a library of plug-in bus protocols to validate their complete system. ARM RealView SoC Designer and SOC-VSP software enable continuous validation of software and hardware from concept through volume production.
more: http://www.carbondesignsystems.com/corpsite/products/html/soc-vsp-product-brief.html |
Carbon Design Systems |
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| Socrates-Spinner |
Socrates Spinner eases I/O Fabric Management. Modern SoC devices typically support multiple static and dynamic operating modes. This can result in thousands of top-level signals that need to be mapped to hundreds of I/O pins according to the target application. Spinner manages this increasingly complex area by specifying and auto-generating all of the logic associated with the chip I/O layer. |
Duolog |
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| Socrates-Weaver |
Socrates Weaver enables rapid IP Integration and Chip Assembly. IP reuse and efficient IP integration are essential for successful SoC development. Weaver is a revolutionary tool for IP integration that is the fastest and most efficient way to build and maintain complex systems. The unique rules-based integration methodology employed by Weaver maximizes the potential for IP, subsystem and system reuse. |
Duolog |
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| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
| Jasper Configurable OCP Proof Kit |
Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you
can generate equivalent property sets for mixed-code environments. |
Jasper Design Automation |
Jay Littlefield |
650-966-0264
ocpinfo@jasper-da.com |
