OCP Compliant EDA Products

The EDA Product Library is provided as a service to OCP-IP members to list IP products they wish to offer as OCP compliant. Contact these providers directly at the e-mail address and phone numbers provided.

Please note that OCP-IP makes no warranties for the products listed on this page.

To submit an OCP compliant EDA Product listing click here.

Product	Description	Provider	Marketing Contact
			Name	Phone/E-mail
imPROVE-HDL	An assertion-based formal verification tool that can be used on a wide range of design blocks. imPROVE-HDL includes a GUI, xshell and script mode which make it very easy to use. The tool can seamlessly fit in a simulation-based verification flow or in a Specman Elite.	AerieLogic	Samuel Dellacherie	+33 (0)2 31 53 30 05 samuel.dellacherie@aerielogic.com
imPROVE-HPK	A formal verification tool dedicated to the automatic verification of hardware designs based on standard protocol interfaces (such as OCP, AmbaAHB, PCI, PCI-X, etc). imPROVE-HPK automatically creates the complete protocol environment of the design and then automatically checks that the protocol properties (including functional performance analysis properties) and coverage scenarios are met.	AerieLogic	Samuel Dellacherie	+33 (0)2 31 53 30 05 samuel.dellacherie@aerielogic.com
OCP Hardware Protocol Kit	The OCP Hardware Protocol Kit has been designed to enable quick and exhaustive verification of any OCP compliant hardware block. The kit automatically creates the complete OCP protocol environment of the design and then automatically checks that the OCP protocol properties (including functional performance analysis properties) and OCP coverage scenarios are met. The OCP HPK covers both the 2.0 and 1.0 versions of the OCP.	AerieLogic	Samuel Dellacherie	+33 (0)2 31 53 30 05 samuel.dellacherie@aerielogic.com
OCP Assertion Based Verification IP	Cadence® Incisive® Assertion-Based Verification IP (ABVIP) for OCP 2.0, 2.1 and 2.2 works together with Cadence's formal and/or dynamic verification engines to increase quality and productivity and provides a predictable path to verification closure. When used together with Incisive Formal Verifier (IFV) the Incisive ABVIP enables design engineers to immediately verify protocol functionality and compliance since no testbench is needed nor must any stimuli be created.	Cadence Design Systems, Inc.	Pete Heller	408-914-6896 peteh@cadence.com
CoWare Model Designer	CoWare Model Designer speeds the concurrent design of SoCs with embedded software at the electronic system level. CoWare Model Designer is a native IEEE 1666 SystemC toolset, providing simulation and debug capabilities for transaction-level modeling. It comes standard with the SystemC Modeling Library (or SCML, based on a foundation of OSCI and OCP-IP standards), user guidelines for modeling reusable transaction level peripherals, and generic IP examples that make learning TLM easier. Together with the CoWare Model Library, the largest IP model library for SystemC, users can rapidly create and validate SoC designs at the transaction level in SystemC.	CoWare, Inc.	Patrick Sheridan	408-392-8528 psheridan@coware.com
CoWare Platform Architect	CoWare Platform Architect speeds the concurrent design of SoCs with embedded software at the electronic system level. CoWare Platform Architect combines hardware/software partitioning and platform assembly together with simulation, debug and analysis capabilities. CoWare Platform Architect provides native IEEE 1666 SystemC support, and comes standard with the SystemC Modeling Library (or SCML, based on a foundation of OSCI and OCP-IP standards), user guidelines for modeling reusable transaction level peripherals, and generic IP examples that make learning TLM easier. Together with the CoWare Model Library, the largest IP model library for SystemC, users can rapidly create and validate SoC designs at the transaction level in SystemC.	CoWare, Inc.	Patrick Sheridan	408-392-8528 psheridan@coware.com
OCP e VC	The OCP e VC 2.0 is an e RM(2.0) compliant verification component providing scalability to the verification environment from block-level to system-level verification. The OCP e VC can be configured as a Master/Slave agent thus enabling verification of Master and/or Slave OCP interface(s) of the of DUT. The OCP e VC will be available mid-October 2003.	eInfochips Inc.	Milind Kapure	408-496-1882 milind@einfochips.com
HCR_9910	Hardware implementation of SHA-256 message-digest algorithm.	HDL Design House	Predrag Markovic	p-markovic@hdl-dh.com
HCV 500 SV	SystemVerilog Assertion Checker for OCP 2.0	HDL Design House	Predrag Markovic	408-496-1882 p-markovic@hdl-dh.com
OCP Assertions Library	The OCP Assertions Library represents a comprehensive, highly configurable, well structured set of OCP v1.0 compliance properties. Using IBM's FoCs tool, the assertions can be leveraged as synthesizable VHDL/Verilog checkers that are easy to integrate in any design. The library defines both compliance and coverage checkers for a reliable verification. Nobug currently works on a PSL version of the library that will transparently work from with Verisity's Specman verification environment. Support for OCP v2.0 is also in works and will be available before the end of the year.	Nobug Consulting Inc.	Moshe Shalev	408-455-5512 moshe@nobug.com
CoreCreator	Core Configuration, Verification and Packaging. OCP 1.0 compliant.	OCP International Partnership	OCP-IP Administration	503-291-2560 admin@ocpip.org
SystemC OCP Transactional Models	SystemC OCP models for Transaction Layer 1 (TL1) and Transaction Layer 2 (TL2).	OCP International Partnership	OCP-IP Administration	503-291-2560 admin@ocpip.org
CoreCreator	Core Configuration, Verification and Packaging.	Sonics, Inc.	Phil Casini	650-605-6131 pcasini@sonicsinc.com
Sonics Studio	Architectural Exploration and SoC Integration Development Environment.	Sonics, Inc.	Phil Casini	650-605-6131 pcasini@sonicsinc.com
OCP2.0e VC	This eVerification Component is fully compliant with the OCP 2.0 specification and expedites creation of a more efficient testbench for each OCP interface in your DUT and works with both Verilog and VHDL devices and with all HDL simulators supported by Specman Elite. The OCP 2.0 e VC can be used for verification of any OCP interface across all levels of abstraction and it is suitable for multi OCP interface systems.	YogiTech SpA	Natale Barsotti	natale.barsotti@yogitech.com

Product	Description	Provider	Marketing Contact
			Name	Phone/E-mail
DesignWare OCP 2.1 Verification IP	Synopsys DesignWare® Verification IP for OCP provides a quick and efficient way to functionally verify OCP 2.1 interfaces. It enables the verification of master and slave devices in OCP systems and cores and provides 100% functional coverage as defined in section 4 of the OCPIP 2.0/2.1 Compliance Checks document. The DesignWare VIP for OCP supports the Verification Methodology Manual for SystemVerilog. It also supports Verilog and VHDL testbenches.	Synopsys Inc	Neill Mullinger	503 547 6048 neill.mullinger@synopsys.com or admin@ocpip.org

Product	Description	Provider	Marketing Contact
			Name	Phone/E-mail
SOC-VSP	Carbon's SOC-VSP software is the first virtual system prototyping solution that combines the power of ARM RealView SoC Designer simulation with Carbons ability to incorporate a designs RTL. Finally, a hardware-accurate, soft-model of a SoC that can be rapidly assembled and functionally validated on an engineers desktop months before silicon. ARM RealView SoC Designer enables System Architects to profile a SoC with end-to-end cycle accuracy including processors, busses, and peripheral models. Now with SOC-VSP software, Verilog and VHDL hardware designs can be added to the list. Software Developers get an early jump on debugging their firmware with an integrated debugger and a hardware-accurate modelrather than waiting months for silicon or an idealized behavioral model to be developed. Hardware Designers can leverage fast mixed-level simulation, an integrated debugger, and a library of plug-in bus protocols to validate their complete system. ARM RealView SoC Designer and SOC-VSP software enable continuous validation of software and hardware from concept through volume production. more: http://www.carbondesignsystems.com/corpsite/products/html/soc-vsp-product-brief.html	Carbon Design Systems	Alan Swahn	781.890.1500 x228 alan@carbondesignsystems.com
Magillem	The Eclipse based Magillem Core is at the heart of a fully featured flow optimization suite comprised of an IP-XACT packager, a platform assembly tool,a complete development environment, a flow control tool and a register view kit. The Magillem suite is a one-of-a-kind innovative software tree, enabling flawless and homogeneous design flow integration for various targets such as ASICs, FPGAs, electronic boards, AMS domain and complex systems. Adaptation kits have been developed for each target. Add-ons are also available to meet specific requirements of customers such as Reporting and Documentation, Safety and Traceability of Critical systems Designs. Key customers applications: specifications, virtual prototyping, verification, validation, legacy integration, management of obsolescence, etc. benefit from a common backbone and seamless encapsulation into one unified environment. MAGILLEM undisputed advantage lies in the extended potential given to users in programming their flow control, effectively integrating various interoperable point tools and developing additional modules for missing functionalities. Flexibility and versatility are provided by the powerful Custom Generators Factory.	Magillem Design Services	Geday	+33.1.40.21.35.50 geday@magillem.com

Product	Description	Provider	Marketing Contact
			Name	Phone/E-mail
Jasper Configurable OCP Proof Kit	Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments.	Jasper Design Automation	Jay Littlefield	650-966-0264 ocpinfo@jasper-da.com
Jasper Configurable OCP Proof Kit	Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments.	Jasper Design Automation	Jay Littlefield	650-966-0264 ocpinfo@jasper-da.com
Jasper Configurable OCP Proof Kit	Jaspers OCP IP Generator produces OCP property suites tailored for specific OCP configurations. The IP Generator leverages the information within the OCP configuration file to tailor the generated properties to only those that are relevant to the specific design under test. Run times are nearly instantaneous, and the resulting output files are available in Verilog® or VHDL flavors. The OCP IP Generator supports property specification in either PSL or SystemVerilog Assertion (SVA) format. This support provides great flexibility not only for use on internally developed OCP blocks, but also with purchased design IP configurations since you can generate equivalent property sets for mixed-code environments.	Jasper Design Automation	Jay Littlefield	650-966-0264 ocpinfo@jasper-da.com