VerificationWorkgroup: OCP-IP has a long-established Functional Verification Working Group (FVWG). The group meets on a regularly scheduled basis and was created to provide or enable tools, models, infrastructures and data, which support industry-leading functional verification of OCP-based designs, as well as drive enhancements to the OCP specification and improve verification. If you are interested in more information about the FVWG or wish to participate in group activities and meetings, please contact us at admin@ocpip.org. Compliance Checks: This document of English language compliance checks formally describes the 'legal' constraints for signals on an OCP interface. The document is available free to OCP-IP members and was developed by the FVWG. Compliance checks eliminate the need for “best guess” verification by engineers, making certain an OCP interface complies with the specification, assuring verification quality and that IP blocks are compatible at the system level. In addition, these checks define a set of rules for the OCP Specification. Constraints can be as simple as "check that a signal is never 0" or may be complex temporal expressions. If no check is violated by functional and/or formal verification, the logic is proven compliant with the protocol. The compliance checks can be used in several different ways. Formal tools can use checks to be sure a design never violates them, proving OCP compliance. They can also use the same checks to cover the number of times a given restraint was hit. Functional verification tools can use the properties to build protocol checkers (inVerilog/VHDL/E/SystemC, etc.). By applying stimuli to the design under test (DUT) and verifying that protocol checkers are not reporting violations, OCP compliance is verified. If you wish to obtain a copy of this document please contact us at admin@ocpip.org. Functional Coverage: Functional Coverage is a technique to measure the quality of the stimuli generated by a verification test suite. It provides an objective view of the verification space and is used to measure the completeness of the verification of an OCP IP block. Guidelines, developed by the FVWG, eliminate the need for “best guess” verification by engineers, making certain an OCP interface complies with the current specification and assuring verification quality and IP block compatibility at the system level. These guidelines are available free to OCP-IP members. To obtain a copy please contact us at admin@ocpip.org. CoreCreator® II: CoreCreator II features verification IP and command-line based tools for validating Open Core Protocol (OCP) implementations, reducing design time and risk, and enabling rapid time to market. CoreCreator II allows users to verify, debug, and analyze OCP cores and OCP-based systems. It is comprised of two fundamental component parts: first, Synopsys’ DesignWare® verification IP provides OCP master and slave transactors that generate and respond to all types of OCP 2.2 transactions, and a simulation monitor that provides coverage reports of the functional coverage groups defined in the Protocol Compliance section of the OCP Specification. Second, Sonics’ performance analyzer (ocpperf2) and disassembler (ocpdis2) measure interface performance and help view the behavior of OCP traffic. Both component parts are configurable to support the wide range of OCP 2.2 interface options. The new version is compatible with traditional Verilog and VHDL testbench environments to create directed tests for OCP designs. Synopsys’ DesignWare verification IP within CoreCreator II adds support for advanced verification methodologies as described in the Verification Methodology Manual for SystemVerilog to enable its use in constrained-random verification environments. CoreCreator II includes support for the existing CoreCreator BFM Verilog task interface allowing members to transition testbenches to the new verification IP with minimal changes to their testbench code.
Members can now request copies
of CoreCreator II as part of the benefits of their membership agreement by
visiting the OCP-IP website at www.ocpip.org
CC II Datasheet: A datasheet is available that provides a concise description of our CoreCreator® II product. This is available from http://www.ocpip.org/socket/datasheets/CoreCreator_II_Datasheet.pdf. CoreCreator®: CoreCreator® is a software design and verification product made available at no charge to OCP-IP members. It provides a single graphical or command-line based environment for validating Open Core Protocol (OCP) implementations and “componentizing” OCP compatible cores. CoreCreator® streamlines the generation and packaging of core models, interfaces, timing parameters, synthesis scripts, test vectors, and verification suites necessary for efficient IP core reuse and SoC integration. Validation and componentization is accomplished through three systematized tasks: (1) validate the OCP implementation, (2) capture the relevant core representations, and (3) package the core for reuse. CoreCreator® also provides an environment for stimulating a core (or multiple cores) and analyzing performance and functionality in a system environment. CoreCreator’s® high degree of automation, featuring tight feedback loops, enables cores to be rapidly componentized to make reuse straightforward and predictable. If you wish to obtain your copy of CoreCreator®, please contact us at admin@ocpip.org. CC Datasheet: A datasheet is available that provides a concise description of our CoreCreator® product. This is available from www.ocpip.org/socket/datasheets/CoreCreator_4.pdf. In addition to this datasheet, a comprehensive training program is available for CoreCreator® users. This training is free to OCP-IP members. To obtain copies, please contact us at admin@ocpip.org. DesignWare Verification IP: DesignWare Verification IP is now included as one of the many benefits of OCP-IP membership! PSL Package: Also available to OCP-IP members is an OCP Property Specific Language (PSL) package to aid in verification of IP blocks. The PSL package compliments traditional verification methodologies. Unlike other methods of verification, the PSL is hardware property, not a verification language. PSL is a consistent, simple, powerful property with a declarative structural syntax. The ordered nature of the language gives it a very low learning threshold, ensuring rapid adoption and implementation. The OCP PSL package contains 4 different layers enabling a sustainable verification environment both immediately and in the future. Both VHDL and Verilog flavors are provided free of charge to OCP-IP members. OCP SystemC Channel: Also available free to members is an OCP
SystemC Transaction Level Monitor (TLM) Channel, including a TL3 channel
based on the OSCI TLM version 1.0. The TL3 provides the ability to model
communication more abstract than bus interface transactions; for example, it
supports message-passing communication. Additionally, this feature
represents unification of OCP and OSCI TLM work. Version 2.1.3 also has a
common access interface for the connection of transaction monitors,
assertion checkers, etc. to the OCP channel at TL1, TL2 and TL3 abstraction
levels. This feature ensures convenient EDA tool support for the OCP
channels. Tools can now be connected to the channel in a modular fashion
without requiring knowledge of internal channel operation. 2.1.3 also includes new features, which improve model interoperability, resulting in better productivity in system level modeling. A regression suite enables OCP-IP to ensure a superior level of testing before releasing the Channel. This version additionally includes a set of fully configurable abstraction layer adapters for TL0 toTL1 and TL1 toTL2. The adapters support full OCP interface right out of the box. This version is fully compliant with SystemC 2.1v1. OCP Interoperability: OCP is a highly configurable core-specific interface, which can be customized for use with virtually any type of IP core. In order to make it easier for the designer to use OCP with a particular core, the OCP Specification provides the capabilities of subsets and profiles. Subsets are typically used when an IP core has only a small subset of the complete OCP configuration. For example, some IP cores only support write operations or read operations. In this case, OCP can be easily configured to only provide these basic capabilities.Profiles are typically used for the case of more complex IP cores. The OCP Profile consists of two parts: 1) a pre-configured OCP interface, and 2) detailed implementation guidelines. These profiles are provided in the OCP Specification for IP cores with a native OCP interface, as well as for legacy IP cores, which already have an existing interface, but need to operate with other IP cores in a system. For example, the use of profiles for legacy cores involves interfaces such as AHB and AXI. By using these pre-configured OCP interfaces, the designer can ensure that these OCP interfaces will smoothly inter-operate with other cores having different OCP interfaces. |
