Community Newsletter: May 2017


IN THIS ISSUE:

 

Message from the Chair

Lu Dai, Accellera Systems Initiative Chair

As I look back at the first half of this year, we have made tremendous progress and have reached some significant milestones:

  • DVCon U.S. concluded its 29th year with more than 1,000 participants over the course of the four-day conference. Of particular note was the tremendous interest in our emerging Portable Stimulus standard. The three-hour Monday morning tutorial kicked off the conference to a user community eager to learn about the progress of the standard and plans for its future. The interest in the tutorial was so great that we recently updated the material and presented a three-part webinar series that is now available online.
  • The success of our first DVCon China last month demonstrates the growing interest in that region for the education and opportunity to connect with colleagues that the DVCon brand provides. More than 200 attendees came to see two keynotes, six tutorials, eight papers, 11 exhibitors and 21 posters. A great start in its inaugural year.
  • In April we announced the IEEE’s approval of IEEE 1800.2 (UVM) as a standard, which will be available later this spring at no charge through the Accellera-sponsored IEEE Get Program.
  • The UCIS Working Group has revitalized its efforts to develop version 2.0. If you are interested in this standard and would like to provide input, the working group welcomes your participation.
  • I’d like to extend a warm welcome to our newest members: ChipGlobe, Cypress Semiconductor and Verific. As our membership continues to grow around the world, we encourage you to join Accellera and participate in our working groups.

As the Design Automation Conference (DAC) approaches, we invite you to join us at our upcoming events. The Portable Stimulus Working Group (PSWG) will present a tutorial that will help attendees understand the value of portable stimulus and how to use it. We will also have our annual breakfast with the presentation of the Accellera Leadership Award, followed by a user-led Town Hall discussion focused on the efforts of the PSWG. There will also be Birds-of-a-Feather meetings for those interested in the developments of the Multi-Language (ML) Working Group and the UCIS Working Group.

I look forward to seeing you at our events at DAC, as well as our upcoming DVCon India and DVCon Europe conferences later this year.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

DACAccellera at DAC

To register for the Design Automation Conference visit the DAC website.

Accellera Breakfast & Portable Stimulus Standard Town Hall

Tuesday, June 20th
7:30am-9:00am
Austin Convention Center, room 10AB

With the emerging Accellera Portable Stimulus early adopter release available just prior to DAC, what can users expect? What’s in the early adopter release? When will Portable Stimulus 1.0 be available? Questions like these and more will be discussed during our user-led Town Hall discussion at the Design Automation Conference. We’ll also be discussing our goals for the early adopter release and what we hope to learn. The Town Hall will be moderated by Tom Fitzpatrick of Mentor Graphics. Participants include: Faris Khundakjie, Intel; Sanjay Gupta, Qualcomm; and Karl Whiting, AMD.

We invite you to join in the discussion following an update by Accellera Chair Lu Dai and the presentation of the Accellera Leadership Award. The Award is given to an individual who has provided active leadership and contributed significantly in the vision of EDA and IP standards development activities and the governance of Accellera Systems Initiative (and/or its precedent organizations).

The Accellera-sponsored breakfast is free to DAC attendees, but registration is required.

A DAC Tutorial: “An Introduction to the Accellera Portable Stimulus Standard”

Monday, June 19th
1:30pm-3:00pm
Austin Convention Center Room 18CD

This tutorial is an introduction to the upcoming standard, starting with background on the intended scope and defining goals. The main concepts behind the standard will be reviewed, including the key semantics underlying the model formats. Portable stimulus is not intended as a replacement for the UVM standard, but rather as a complement to it. The tutorial provides guidance on when and where the new methodology can be applied for maximum benefit on a chip project.

Registration with the Design Automation Conference is required to attend the tutorial. Find out more about the tutorial here.

Multi-Language Verification Working Group Birds-of-a-Feather

Tuesday, June 20th
3:00pm – 4:00pm
Austin Convention Center, Room 9C

The Multi-Language Verification Working Group has been working towards a standard to simplify verification scenarios that involve integrating DV code that has been written in different frameworks. During the Birds-of-a-Feather session we will discuss the architecture of the overall solution as well as the beginnings of the reference implementation. Join us to learn more about this evolving standard and to connect with colleagues interested in its development.

The meeting is free for DAC attendees, but registration is required.

Unified Coverage Interoperability Standard (UCIS) Birds-of-a-Feather

Tuesday, June 20th
1:00pm – 2:00pm
Austin Convention Center, Room 9C

The UCIS Working Group invites you to join a meeting at DAC for an open discussion on coverage closure challenges such as exclusions, waivers, and efficient ways to track coverage during the life cycle of project. Coverage from formal verification and supporting UCDB generation for code coverage and functional coverage on emulation platforms, including UCIS XML-based flow for merging coverage data across vendors, will be addressed. We will also look at how to refine UCIS to enable seamless merging of code coverage and functional coverage data via a common coverage database model.

The meeting is free for DAC attendees, but registration is required.

 

DVCon around the Globe

DVCon is the industry’s premier set of conferences for discussion of the functional design and verification of electronic systems.

DVCon U.S. 2017

DVCon U.S.

DVCon U.S. 2017 concluded its 29th annual successful conference and exhibition in San Jose, California with a sold-out exhibition and many in-depth technical tutorials, panels, and poster sessions for attendees to choose from over the course of the four-day program. “DVCon’s popularity to the practicing design and verification engineer continues to be unmatched,” stated Dennis Brophy, DVCon U.S. General Chair. “As we share best practices on electronic system design and verification, and foster discussion on current and emerging standards and technology, the DVCon conferences have become the must-attend events to learn about state-of-the-art methods.”

Save the date: DVCon U.S. 2018 will be held February 26-March 1 at the DoubleTree Hotel in San Jose, California. The call for abstracts will be available July 13th with abstracts due by August 8th. Tutorial and panel proposals will be accepted August 16th through September 29th.

DVCon China 2017DVCon China

DVCon China held its first conference and exhibition last month in Shanghai where attendees were presented with two keynotes, six tutorials, eight technical presentations and 21 poster sessions. There was also an exhibition where attendees could to learn about the latest products and connect with colleagues. Bin Liu of Intel was presented with the Best Paper Award for his paper, “Best Practices over Enhancing SoC Verification Efficiency.” Vinoth Kumar Subramani of Altran Group received the Best Poster Award for his poster, “On the Fly Stimulus Generation for Coverage-Driven Functional Verification based on Constraint Random.”

DVCon India 2017DVCon India

The 4th annual DVCon India will be held September 14th and 15th at the Leela Palace in Bangalore. Similar to previous years, the conference provides two tracks: ESL and Design & Verification (DV). The ESL track is targeted toward the adoption of SystemC in the semiconductor industry, and the DV track provides a platform for engineers to share experiences and best practices on design and verification. For more information on the DVCon India program, visit the conference website.

DVCon Europe 2017DVCon Europe

The 4th annual DVCon Europe will be held October 16th and 17th at the Holiday Inn Munich City Centre in Munich, Germany. “DVCon Europe continues to be a great success, with attendance at the 2016 show up 20% over previous year,” stated DVCon Europe General Chair Oliver Bell. “It's fantastic how quickly the conference has become established as the European engineering community’s ‘place to be.’ The event is truly made for engineers by engineers.”

We are delighted to announce two very impressive and influential keynote speakers for the 2017 conference. On Monday, October 16th, Dr. Horst Symanzik, Director of Integrated Circuit Engineering at Bosch Sensortec, will be talking about the latest challenges faced by his teams on some of the most high-end designs being performed in Europe. On Tuesday, October 17th, the well-known technologist Berthold Hellenthal, Head of the Progressive Semiconductor Program at Audi AG, will consider the latest challenges he sees on the horizon in the ever evolving automotive space. For more information about DVCon Europe, visit the conference website.

 

SystemC Evolution Day

SystemC Evolution Day 2017With the success of the first SystemC Evolution Day in 2016, the second full-day technical workshop will be held October 18, 2017 in Munich, Germany. In several in-depth sessions, current and future standardization topics regarding SystemC will be discussed in order to accelerate their progress for Accellera and IEEE standard’s inclusion. SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and Accellera working groups to advance the SystemC standards in a full-day workshop. A Call for Contributions for Lightening Talks has been issued with a deadline of June 30, 2017. Find out more >

 

The Taiwan Forum for System Level Verification & Design

The Taiwan Forum for System Level Verification & Design was held last month in Hsinchu City. The keynote by Dr. Kazutoshi Wakabayashi, a well-known figure in the Japan industry and academy, illustrated how Japan professionals and researchers use high-level synthesis to realize IoT and AI applications in FPGAs. Three tutorials were featured to introduce the latest concepts and technologies in SoC verification, high-level synthesis and the emerging portable stimulus standard. A special session by EDA vendors provided a look at unique methodologies in IC design and verification. Copies of the presentations are available for download.

 

Portable Stimulus Webinar Series

Our three-part webinar series on Portable Stimulus is now available on demand. Derived from the Accellera Portable Stimulus Tutorial presented at DVCon U.S. in February 2017, the "Creating Portable Stimulus Models with the Upcoming Accellera Standard" tutorial series provides an in-depth look at the upcoming standard that will permit the creation of a reusable model for a variety of users across different levels of integration under different configurations.

Part 1 begins with a discussion of verification productivity, the reasons the Portable Stimulus standard was undertaken and the goals of the standardization effort. It also provides a detailed technical overview of many of the concepts and language constructs being used to enable portable scenario-level specification of stimulus and verification intent.

Part 2 builds on the previous discussion in Part 1 of concepts and constructs, showing how block-level stimulus and verification intent models can be reused and augmented to describe system-level scenarios. It also discusses how a Portable Stimulus model may be used to generate a test implementation on multiple platforms.

Part 3 discusses how to model coverage in PSS and how a hardware/software interface layer could be used to improve portability of stimulus models.

 

IP-XACTQ & A with IP-XACT Working Group Chair, Erwin de Kock

Q: What are the key issues your working group is currently addressing?
A: One key issue currently is the development of an IP-XACT user guide. At the moment, there is no user documentation. We have the IEEE 1685 specification and the XML schema, but they do not provide a user perspective on the standard. We aim to promote the use of the IP-XACT standard by providing a user guide that explains the standard from a user’s point of view.

Q: What do you see happening with IP-XACT over the next 6-12 months?
A: Our goal is to complete the user guide within the next six months. After that, we plan to start working on a new revision of the IEEE 1685 standard. There are two revisions dated 2009 and 2014. It is time to start the work on a new IEEE 1685 revision, targeting the end of 2019 / beginning 2020 for completion.

Q: Can you tell us about the new IP-XACT Community?
A: We recently added the IP-XACT Community to the Accellera website so that those interested in the standard would have access to the latest information. The IP-XACT forum is a good resource and an excellent place for discussion as we work on the revision. To ensure we’re developing the standard to meet user requirements, we’d like to see more companies join the IP-XACT ecosystem: IP provider and SoC integration companies as well as system companies.

Q: What else would you like readers to know about IP-XACT?
A: We’ll begin collecting requirements for the new revision of the IP-XACT standard, and we’d like discussion in the community about what people would like to have included. Those requirements need to be motivated with use cases and commitments to implement and validate them before we can include them in the new revision. Companies are invited to join the IP-XACT WG to contribute.

 

UVMIEEE 1800.2 for UVM has been approved as an IEEE Standard

IEEE 1800.2™ Standard for Universal Verification Methodology (UVM) has been approved by the IEEE Standards Association (IEEE-SA). The standard is now available for download at no charge under the Accellera-sponsored IEEE Get Program. Read the press release >

 

 

2017 Global Sponsors

CadenceMentor GraphicsSynopsys

Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.

 

Copyright 2017 Accellera Systems Initiative