Automatic Synthesis for Network-on-Chip

The automatic synthesis of an efficient communication topology for a network-on-chip (NoC) is a critical and challenging design task.  Given a target execution-platform library and a set of end-to-end communication constraints, which include throughput and latency requirements, the optimization problem is to find an optimal topology that satisfies the constraints by assembling efficient component instances from the library. In fact, the synthesis algorithm must respect several other design constraints, including: network operating frequency, maximum number of input/output ports per router, area constraints, deadlock avoidance conditions and limited space to install the communication infrastructure.  The objective function of the optimization task is typically a combination of dynamic power consumption and installation costs like leakage power and area.

At the University of California at Berkeley and in collaboration with Prof. Luca Carloni of Columbia University, we have developed "CoSI NoC", a synthesis tool that addresses this problem. In our approach, the platform is characterized using detailed physical models for on-chip links, routers and network interfaces. Then, the chip floor-plan is performed to define regions where communication components can be installed. Finally, the synthesis step returns a register-transfer level implementation of the synthesized network in SystemC format.  The first release of "CoSI NoC" is expected to be available in early 2007.

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