Automated Formal Verification of OCP-based IPs Using Cadence's OCP VIP Library

In today’s SoC development, high mask costs exacerbate the need for first-pass silicon. The steep growth of verification complexity combined with shortened time to market requirements, necessitates a search for more efficient and automated verification practices.

The automation of Formal Verification (FV) is one possible solution to address the above problems. Complementary to well-established pseudo-random verification techniques, FV enables the verification engineer (or the designer) to exhaustively prove specific parts of a circuit. This paper discusses the automation of FV for bus protocols like OCP.

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