Products Using OCPMIPS combines multi-threading with coherent multicore IP as a product implementation proof point for OCP 3.0 New Option for the Embedded Market Claiming a new option for the embedded market, MIPS Technologies is rolling out a multi-threaded, multi-processor licensable intellectual property (IP) core. The four-processor MIPS32 1004K Coherent Processing System (CPS) claims ease of programming and significant performance advantages. MIPS 32 1004K CPS The MIPS 32 1004K CPS includes one to four configurable 1004K cores, a Coherence Manager for managing operations between the cores and I/O, a hardware I/O Coherence Unit, a Global Interrupt Controller, and a 256-bit interface to an optional Level 2 (L2) cache controller. The 1004K CPS, available in June, will be delivered as RTL code with synthesis scripts for Synopsys, Cadence Design Systems, and Magma Design Automation flows. |
