Synopsys Verification IP for the OCP Interface

Synopsys has expanded its portfolio of DesignWare® Library intellectual property (IP) with the release of verification IP for the Open Core Protocol (OCP) interface. OCP is a common standard IP core interface, or socket, that facilitates "plug and play" system-on-chip (SoC) design. Synopsys developed the verification IP for the OCP interface in response to customer demand for using the DesignWare Library and VCS® Verification Library to verify systems and cores that utilize OCP.

The addition of OCP 2.1 to the portfolio enables the verification of OCP cores, OCP systems, mixed OCP/AMBA systems, and OCP systems to their external interfaces. The OCP verification IP provides 100 percent coverage as defined in section 4 of the OCP 2.0/2.1 Compliance Checks document. It is compliant with the popular VMM methodology defined in the Verification Methodology Manual for SystemVerilog, enabling easy integration with constrained-random, coverage-driven environments; it also supports Verilog and VHDL testbenches. The OCP Verification IP supports all popular simulators and enables up to five times faster verification when used with the VCS comprehensive functional verification solution.

To view the Synopsys press release, click here.