VDEC Simple Bus IP

VLSI Design and Education Center (VDEC), a part of the University of Tokyo, is currently developing a simple bus IP based on OCP.  The IP being developed is being used in a current project whose objective is to develop a SoC design platform.

The VDEC team has already defined the detailed specification of the bus IP and has begun designing the RTL.

In addition to the simple bus IP, VDEC is developing many OCP-based cores such as processor, RF communication, digital circuits, etc. as a part of the project.  The project plan calls for these cores to be available to VDEC users through the VDEC website after they are designed and well-tested.

VDEC plans to have the project completed and available to VDEC members in Q1 2007.  For more information visit www.vdec.u-tokyo.ac.jp.

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