A Socket-Based uController Design
By Adam Levinthal, General Manager, ASSP Unit, eASIC Corp.
The FlexASIC™ structured-ASIC products are design as
general-purpose configurable logic devices with standard-cell speed, density
and production costs, and FPGA ease of use and prototype costs. Each member
of the FlexASIC product family contains an embedded 8051-based uController.
This uController, called ‘eMu,’ performs built-in self test (Logic and RAM
BIST, etc.) and device configuration of the FlexASIC at system reset. After
reset, eMu implements a number of system-level functions (power management,
clock control, etc.) for the FlexASIC user design.
eMu was designed using a modular design approach based on the Open Core
Protocol (OCP) interface standard. All eMu modules interface through OCP
sockets and are interconnected through a switch fabric created with OCP
merge and split modules. The socket-based design approach provided numerous
benefits during the design and implementation process, allowing the entire
design to be created, from architectural specification to tapeout, in 12
weeks.
The entire FlexASIC FA1 structured-ASIC product was designed between
December 2003 and mid-March 2004. The eMu uController design was one of
eight basic modules in the FlexASIC design. The use of a commercial
uController core (the Flex8051) and OCP socket connections to all
peripherals, as well as uController-based testing written in C, allowed
design and testing of individual modules in eMu to occur in parallel. The
ability to reuse unit tests in the full-module final testbench, using a
top-level test sequencer, eliminated the need for additional full-chip test
development. The entire process represents a streamlined approach to
uController-based ASIC design.
About eASIC
eASIC has developed a breakthrough Structured ASIC technology aimed at
dramatically reducing the overall fabrication cost and time of customized
high-performance semiconductor chips. eASIC’s technology enables rapid and
low-cost ASIC and System-on-Chip designs by its innovative use of proven
programmable logic fabric in conjunction with single-via customizable
segmented routing. As single-via generates ten times higher throughput of
Direct-write e-Beam customization, it enables eASIC to offer NREfree
Structured ASIC. The Structured eASIC technology was successfully proven in
silicon and validated by world-class semiconductor vendors.
Further information about eASIC can be found at www.easic.com.
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