Products Using OCP

Synapse™ 3220 SMART Interconnect IP™

The industry's first non-blocking peripheral interconnect that guarantees end-to-end performance by managing the data, control and test flows between all cores it connects. Using patented protocols and architecture, the Synapse 3220 provides low latency access to a large number of physically dispersed target cores. Synapse 3220 has close links to the physical domain through import and export of data to industry standard floor planner tools. This, plus the pre-verified nature of the Synapse 3220, eliminates the uncertainties around timing closure, often reducing the time to timing closure by more than half. Synapse 3220 has built-in security access mechanisms to create an on-chip "firewall" that facilitates a more secure and robust system. Due to its unique set of features and high degree of automation, it can be rapidly implemented as a peripheral interconnect for a proprietary bus or SiliconBackplane™ based main interconnect. The Synapse 3220 supports IP cores using the industry standard OCP (Open Core Protocol) socket, as well as the APB (AMBA Peripheral Bus) interface for legacy IP cores.

SiliconBackplane™ MicroNetwork

SiliconBackplane MicroNetwork is semiconductor intellectual property (IP) licensed for use in SOC applications. It is an on-chip communications structure that guarantees end-to-end performance by managing all the data, control and test flows on an SOC. SiliconBackplane delivers a fast, highly-efficient, application-specific, on-chip communications network. SiliconBackplane provides a unique combination of highly-scalable raw performance with highly-efficient usable performance. The SiliconBackplane leverages scalable pipelines and configurable data widths to deliver both the highest throughput and lowest latency solution at any given operating frequency. It manages the complex data and control flows generated by multiple initiators such as general purpose microprocessors, DSPs and special purpose hardware accelerators such as MPEG, DMA or packet processors. SiliconBackplane supports IP cores using the industry standard OCP (Open Core Protocol) socket.

MemMax™ Memory Scheduler

The MemMax™ Memory Scheduler provides SOC designers with unparalleled control over memory sub-systems that are now inefficiently shared by multiple, contentious on-chip initiators such as processors and DSP's. Positioned between any standard memory controller interfaced with the industry standard OCP interface and the Sonics SiliconBackplane MicroNetwork™, the MemMax scheduler utilizes the initiator and task information supplied through the SiliconBackplane MicroNetwork to appropriately schedule memory transactions for maximum off-chip DRAM efficiency and utilization while satisfying each initiator’s quality of service (QoS) needs.

Sonics Studio™

Sonics Studio is a development environment used to speed every stage of System-On-Chip (SOC) design. From architectural exploration to GDSII, Sonics Studio provides an array of graphical and command line based tools and utilities that provide the SOC architect and designer a single environment within which the entire SOC can be assembled, configured and a Netlist generated.

For more information about Sonics, visit www.sonicsinc.com. 

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