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Design Methodologies References
Optimization, Synthesis and Design Space Exploration | Sockets, Interfaces and Reuse
| Title |
Author(s) |
Presented |
Published |
Date |
Page(s) |
| A Communication-Centric Design Flow for HIBI-based SoC's |
T. Kangas, J. Riihimaki, E. Salminen, V. Lahtinen, H. Orsila, K. Kuusilinna, T.D. Hamalainen, S. Vassiliadis |
|
LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS) |
2004 |
474-483 |
| A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration |
A. Baganne, I. Bennour, M. Elmarzougui, R. Gaiech, and E. Martin |
Design Automation and Test in Europe (DATE) 2003 |
|
March 3-7, 2003 |
pp. 250-255 |
| A Power and Performance Model for Network-on-Chip Architectures |
N. Banjerjee, P. Vellanki, K.S. Chatha |
Design Automation and Test in Europe (DATE) 2004 |
Proceedings, DATE 2004 Volume: 2 |
February 16-20, 2004 |
1250-1255 |
| A Practical Tool Box for System Level Communication Synthesis |
D. Hommais, F. Petrot, I. Auge |
9th CODES 2001 |
Proceedings, CODES 2001 |
April 25-27, 2001 |
48-53 |
| A Simulation Based Approach for Incorporating Virtual Components IP Cores into Multimedia Systems De |
A. Baganne, I. Bennour, M. Elmarzougui, E. Martin |
IEEE ICASSP 2003 |
Proceedings, ICASSP 2003, Volume: 2 |
April 6-10, 2003 |
525-528 |
| A Simulation-based Power-aware Architecture Exploration of a Multiprocessor System-on-Chip Design |
F. Menichelli, M. Olivieri, L. Benini, M. Donno, L. Bisdounis |
Design Automation Test in Europe (DATE) 2004 |
Proceedings, DATE 2004 Volume: 3 |
February 16-20, 2004 |
312-317 |
| Addressing the System-on-a-Chip Interconnect Woes Through Communication-based Design |
M. Sgroi, M. Sheets, A. Mihal, K. Kuetzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli |
Design Automation Conference (DAC) 2001 |
Proceedings, DAC 2001 |
2001 |
667-672 |
| An Efficient Architecture Model for Systematic Design of Application-specific Microprocessor SoC |
A. Baghdadi, A.A. Jerraya, D. Lyonnard, N.E. Zergainoh |
Design, Automation and Test in Europe (DATE) 2001 |
Proceedings, DATE 2001 |
2001 |
55-62 |
| An interconnect channel design methodology for high performance integrated circuits |
V. Chandra, A. Xu, H. Schmit, L. Pileggi |
Design Automation and Test in Europe (DATE) 2004 |
Proceedings, DATE |
February 16-20, 2004 |
Vol. 2 pp. 1138-1143 |
| Bandwidth-Constrained Mapping of Cores onto NoC Architectures |
S. Murali, G. DeMicheli |
Design Automation Test in Europe (DATE) 2004 |
Proceedings, DATE 2004 Volume: 2 |
February 16-20, 2004 |
896-901 |
| Benchmark-based design strategies for single chip heterogeneous multiprocessors |
J.M. Paul, D.E. Thomas, A. Bobrek |
Proceedings of international conference on Hardware/software codesign and system synthesis (CODES) |
|
September 8-10, 2004 |
pp. 54-59 |
| Bus Architecture Synthesis for Hardware-Software Co-design of Deep Submicron Systems on Chip |
N. Thepayasuwan, V. Damle, A. Doboli |
21st International Conference on Computer Design |
Proceedings, 21st International Conference on C.D. |
October 13-15, 2003 |
126-133 |
| Combining a Performance Estimation Methodology with a Hardware/software Codesign Flow Supporting Mul |
A. Baghdadi, W.O. Cesario, A.A. Jerraya, N.-E. Zergainoh |
|
IEEE Transactions on Software Engineering, Volume: 28, Issue 9 |
September 2002 |
822-831 |
| Communication analysis for system-on-chip design |
A. Siebenborn, O. Bringmann, W. Rosenstiel |
DATE 2004 |
|
16-20 Feb. 2004 |
Vol.1 pp. 648 - 653 |
| Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization |
G. Varatkar, R. Marculescu |
International Conference on Computer Aided Design (ICCAD) 20 |
Proceedings, ICCAD 2003 |
November 9-13, 2003 |
pp. 510 - 517 |
| Design of High-Performance System-on-Chips Using Communication Architecture Tuners |
K. Lahiri, A. Raghunathan, G. Lakshminarayana, S. Dey |
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits; Volume 23, Issue 5 |
May 2004 |
620-636 |
| Design Space Exploration for Optimizing System-on-Chip Communication Architectures |
K. Lahiri, A. Raghunathan, S. Dey |
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits; Volume 23, Issue 6 |
June 2004 |
952-961 |
| Developing Architectural Patforms: a Disciplined Approach |
A. Mihal, C. Kulkarni, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Yujia Jin, K.Keutzer, K. Vissers, C. Sauer, S. Malik |
|
IEEE Design & Test of Computers, Volume: 19, Issue: 6 |
November-December 2002 |
6-16 |
| Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks |
Li Shang, Li-Shiuan Peh, and Niraj Jha |
|
Symp. on High Performance Computer Architecture (HPCA) |
8-12 Feb. 2003 |
105 - 116 |
| Early ISS Integration Into Network-on-Chip Designs |
A. Wieferink, M. Doerper, T. Kogel, R. Leupers, G. Asceid, H. Meyr |
|
LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS) |
2004 |
443-451 |
| Exploiting the Routing Flexibility for Energy/perf. Aware of Mapping of Regular NoC Architectures |
Jingcao Hu, R. Marculescu |
Design Automation and Test in Europe (DATE) 2003 |
Proceedings, DATE 2003 |
March 3-7, 2003 |
688-693 |
| Fast exploration of parameterized bus architecture for communication-centric SoC design |
C. Shin, Y-T. Kim, E-Y. Chung, K-M. Choi, J.-T. Kong, S. Eo |
Design Automation and Test in Europe Conference and Exhibition (DATE) |
|
February 16-20, 2004 |
Vol. 1, 352 - 357 |
| Floorplan-aware automated synthesis of bus-based communication architectures |
S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane |
Proc. of Design Automation Conference (DAC) |
|
13-17 June 2005 |
pp. 565 - 570 |
| High-level Specification and Automatic Generation of IP Interface Monitors |
M.T. Oliveira, A.J. Hu |
Design Automation Conference (DAC) 2002 |
Proceedings, DAC 2002 |
June 10-14, 2002 |
129-134 |
| Interface Design Approach for System on Chip Based on Configuration |
I. Maalej, G. Gogniat, M. Abid, J.L. Philippe |
International Symposium on Circuits and Systems (ISCAS) 2003 |
Proceedings, ISCAS Volume: 5 |
May 25-28, 2003 |
V-593-596 |
| Linear-Programming-Based Techniques for Synthesis of Network-on-Chip Architectures |
Srinivasan, K.; Chatha, K.S.; Konjevod, G., |
IEEE Transactions on VLSI |
Volume 14, Issue 4 |
April 2006 |
407- 420. |
| Managing Power Consumption in Networks-on-Chips |
T. Simunic, S.P. Boyd, P. Glynn, |
|
IEEE Transactions on Very Large Scale Integration (VLSI)Syst |
January 2004 |
96-107 |
| NoC synthesis flow for customized domain specific multiprocessor systems-on-chip |
D. Bertozzi, A. Jalabert, Srinivasan Murali, R. Tamhankar, S. Stergiou, L. Benini, G. De Micheli |
IEEE Transactions on Parallel and Distributed Systems |
|
Feb 2005 |
Vol. 16, Iss. 2; pp 113-129 |
| NoCGEN: A Template Based Reuse Methodology for Networks-on-Chip Architecture |
J. Chan, S. Parameswaran |
17th International Conference on VLSI Design |
Proceedings, Conference on VLSI Design 2004 |
January 5-9, 2004 |
717-720 |
| OCCN: A Network-on-Chip Modeling and Simulation Framework |
M. Coppola, S. Curaba, M.D. Grammatikakis, G. Maruccia, F. Papariello |
Design Automation Test in Europe (DATE) 2004 |
Proceedings, DATE 2004 Volume: 3 |
February 16-20, 2004 |
174-179 |
| Optimizing Network Throughput: Optimal Versus Robust Design |
P. Lopez, R. Alcover, J. Duato, L. Znica |
Seventh Euromicro Workshop on Parallel and Distributed Proce |
|
February 3-5, 1999 |
45-52 |
| Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets |
H. Blume, T. von Sydow, T.G. Noll |
|
LNCS 3133 Computer Systems: Architectures, Modeling and Simulation (SAMOS) |
2004 |
484-493 |
| Platform-based Design for Digital Signal Processing Systems: a Case Study of MPEG-2/JPEG2000 Encoder |
P. Coussy, A. Baganne, E. Martin |
IEEE 2002 International Conference on Circuits and Systems |
Volume 2 |
June 29-July 1, 2002 |
1361-1366 |
| Power-driven Design of Router Microarchitectures in On-chip Networks |
Hangsheng Wang, Li-Shiuan Peh and Sharad Malik |
|
Proceedings of MICRO 36, San Diego |
Nov 2003 |
pp. 105 - 116 |
| Socket-Based Design Using Decoupled Interconnects |
D. Wingard |
|
ESSIRC from "Interconnect-Centric Design for SoC and NoC" tu |
September 2003 |
|
| SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs |
S. Murali, G. De Micheli |
Design Automation Conference (DAC) 2004 |
|
2004 |
pp. 914 - 919 |
| Synthesis of Communication Interface for SoC Using VSIA Recommendations |
G. Cyr, G. Bois, M. Aboulhamid |
Design Automation and Test in Europe (DATE) 2001 |
Proceedings, DATE 2001 |
2001 |
155-159 |
| Tiles - An Architectural Abstraction for Platform-Based Design |
D. Wingard |
EDA Vision |
|
June 2002 |
|
| Topology Optimization for Application-specific Networks-on-chip |
T. Ahonen, D.A. Sigenza-Tortosa, H. Bin, J. Nurmi |
International Workshop on System-Level Interconnect Prediction (SLIP) |
|
2004 |
53-60 |
| Towards a communication characterization methodology |
S. Chodnekar, V. Srinivasan, A.S. Vaidya, A. Sivasubramaniam, C.R. Das |
Third International Symposium on High-Performance Computer Architecture |
|
1-5 Feb. 1997 |
pp. 310-319 |
| UML-based Multi-Processor SoC Design Framework |
T. Kangas |
|
ACM Transactions on Embedded Computing Systems, Vol. 5, No. 2 |
May 2006 |
281-320 |
| VC Rating and Quality Metrics: Why Bother? [SoC] |
P. Bricaud |
ISQED 2002 |
Proceedings, ISQED 2002 |
March 8-21, 2002 |
257-260 |
| xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-processor SoCs |
M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini |
21st International Conference on Computer Design, 2003 |
Proceedings, 21st International Conference on C.D. |
October 13-15, 2003 |
536-539 |
| xpipesCompiler: a Tool for Instantiating Application Specific Networks on Chip |
A. Jalabert, S. Murali, L. Benini, G. DeMichel |
Design Automation and Test in Europe (DATE) 2004 |
Proceedings, DATE 2004 Volume: 2 |
February 16-20, 2004 |
884-889 |
 |
| Title |
Author(s) |
Presented |
Published |
Date |
Page(s) |
| A Switch Wrapper Design for SNA On-Chip-Network, |
J. Chang, J. Yi, J. Kim |
|
Lecture Notes in Computer Science, Vol. 3740, |
Oct. 2005, |
405 - 414 |
| AHB-Lite overview |
ARM Ltd. |
|
ARM SDVI 0044A |
2001 |
6 pages |
| AIRbus Interface Functional Specification, version 1.0 |
Altera Corporation |
|
Document Identifier A-FS-09-01 |
December 22, 2000 |
8 pages |
| AMBA: Enabling Reusable On-Chip Designs |
D. Flynn |
IEEE Micro |
Volume: 17, Issue 4 |
July-August 1997 |
20-27 |
| An Approach to PVCI-based Wrapper Design |
S. Zhang, M. Gao, Y. Hu, L. Li |
5th International Conference on ASIC |
Proceedings, 5th International Conference on ASIC Volume: 1 |
October 2003 |
433-437 |
| An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive... |
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed A. Jerraya, |
Design Automation Conference archive (DAC) |
|
June 07 - 11, 2004 |
250 - 255. |
| An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip |
Bjerregaard, S. Mahadevan, R.G. Olsen, J. Sparsoe |
International Symposium on System-on-Chip, 15-17 Nov. 2005 |
Tampere, Finland |
2005 |
171 - 174 |
| Applying the OpenMORE Assessment Program for IP Cores |
J.-P. Gueguen, P. Bricaud |
First ISQED |
Proceedings ISQED 2000 |
March 20-22, 2000 |
379-381 |
| Atlantic Interface Functional Specification, v3.0 |
Altera Corporation |
|
|
June 2002 |
10 pages |
| Bridge over troubled wrappers:automated interface synthesis |
V. D'silva, S. Ramesh, A. Sowmya |
|
Proceedings. 17th International Conference on VLSI Design |
2004 |
pp. 189- 194 |
| Comparison of Hardware IP Components for System-on-Chip |
E. Salminen, K. Kuusilinna, T.D. Hamalainen |
International Symposium on System-on-Chip |
|
November 16-18, 2004 |
69-73 |
| Comprehensive Interconnect BIST Methodology for Virtual Socket Interface |
Chauchin Su; Yue-Tsung Chen |
7th Asian Test Symposium (AST) 1998 |
Proceedings AST 1998 |
December 2-4, 1998 |
259-263 |
| Design of a Virtual Component Neutral Network-on-Chip Transaction Layer |
Philippe Martin |
DATE 2005 |
|
2005 |
336-337 |
| Effcient on-chip communications for data-flow IPs |
A. Fraboulet, T. Risset |
|
Proceedings. 15th IEEE International Conference on Applicati |
27-29 Sept. 2004 |
pp. 293 - 303 |
| Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocol |
W.-D. Weber |
IP 2000 System-on-Chip Conference |
Proceedings, IP 2000 System-on-Chip Conference |
March 20-22, 2000 |
|
| Essential Issues for IP Reuse |
D. Gajski, A.C.-H Wu, V. Chaiyakul, S. Mori, T. Nukiyama, P. Bricaud |
Asia & S. Pacific Design Automation Conference ASP-DAC 2000 |
Proceedings ASP-DAC 2000 |
January 25-28, 2000 |
37-42 |
| Experiments with the Peripheral Virtual Component Interface |
R.L. Lysecky, F. Vahid, T.D. Givargis |
13th International Symposium on System Synthesis (ISSS) 2000 |
Proceedings, 13th ISSS 2000 |
September 20-22, 2000 |
221-224 |
| Interface-based Design |
J.A.. Rowson, A Sangiovanni-Vincentella |
Design Automation Conference (DAC) 1997 |
Proceedings DAC 1997 |
June 9-13, 1997 |
178-183 |
| IP Interface Semiconductor Reuse Standard (SRS) |
Motorola Inc. |
|
SRS04IPI V2.0 |
1999 |
148 pages |
| IP Reuse Creation for System-on-a-Chip Design |
P. Bricaud |
IEEE Custom Integrated Circuits Conference (CICC) 1999 |
Proceedings CICC 1999 |
1999 |
395-401 |
| IP Reuse in the System-on-Chip Era |
W. Savage, J. Chilton, R. Camposano |
13th International Symposium on System Synthesis (ISSS) 2000 |
Proceedings, 13th ISSS 2000 |
September 20-22, 2000 |
2-7 |
| MicroNetworks for Flexible SoC Platforms |
D. Wingard |
Sophia Antipolis Forum on MicroElectronics (SAME) 2000 |
Proceedings, SAME 2000 |
October 2000 |
|
| Midbus Interface Functional Specification, v1.1 |
Altera Corporation |
|
|
February 23, 2001 |
10 pages |
| Open Core Protocol Specification v1.0 |
OCP International Partnership (OCP-IP) |
|
|
September 2001 |
201 pages |
| Open Core Protocol Specification, v2.0 |
OCP International Partnership (OCP-IP) |
|
|
September 2003 |
210 pages |
| Open Microprocessors Systems Initiative, PI-Bus VHDL Toolkit Version 3.1 |
M. Bassett, P. Lister, University of Sussex |
|
Open Micro-processor Systems Initiative (OMI) Concertation M |
November 8-9, 1994 |
|
| Reuse Methodology Manual: for System-on-a-Chip Designs |
M. Keating, P. Bricaud |
|
ISBN:0-7923-8175-0, Kluwer Academic Publishers Norwell, MA, |
1998 |
224 |
| Standards for System-level Design: Practical Reality or Solution in Search of a Question? |
C.K. Lennard, P. Schaumont, G. de Jong, A. Haverinen, P. Hardee |
Design, Automation and Test in Europe (DATE) 2000 |
Proceedings, DATE 2000 |
March 27-30, 2000 |
576-583 |
| Surviving the SoC Revolution: A Guide to Platform-based Design |
H. Chang, L. Cooke, M. Hunt, G. Martin, A.J. McNelly, L. Todd |
|
Kluwer Academic Publishers, Norwell, MA, USA |
1999 |
|
| System-level Design: Orthogonalization of Concerns and Platform-based Design |
K. Keutzer, A.R. Newton, J.M. Rabaey, A. Sangiovanni-Vincentelli |
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits; Volume: 19, Issue: 12 |
December 2000 |
1523-543 |
| Testing Reusable IP: A Case Study |
P. Harrod |
International Test Conference (ITC) 1999 |
Proceedings, ITC 1999 |
September 28-30, 1999 |
148 pages |
| Thermal-aware IP virtualization and placement for networks-on-chip architecture |
W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, M.J. Irwin |
|
Proceedings of IEEE International Conference on Computer Des |
11-13 Oct. 2004 |
pp. 430 - 437 |
| Virtual Component Interface Standard |
Virtual Socket Interface Alliance (VSIA) |
|
OCB Specification 2, Version 1.0, 2000 |
2000 |
|
| VSIA Quality Metrics for IP and SoC |
M. Birnbaum, C.C. Johnson |
ISQED 2001 |
Proceedings on ISQED 2001 |
March 26-28, 2001 |
279-283 |
| VSIA Technical Challenges |
H. Sachs, M. Birnbaum |
IEEE Custom Integrated Circuits Conference 1999 |
Proceedings CICC 1999 |
May 16-19, 1999 |
619-622 |
| VSIA: It's Advantages from Four Different Perspectives |
L.H. Cooke |
Custom Integrated Circuits Conference (CICC) 1997 |
Proceedings CICC 1997 |
May 5-8, 1997 |
107-111 |
|
Please contact research@ocpip.org
with questions or suggestions.
|
