Opportunities for CollaborationOCP-IP has a robust infrastructure that includes six highly active technical Working Groups (WGs). Occasionally, there are topics under consideration by the WGs that require additional research and exploration beyond the typical scope of the WG itself. This page is where OCP-IP will post any open opportunities for universities and research groups to collaborate with our technical WGs. If you are interested in more information about potential collaboration, please contact us at research@ocpip.org. Please include the following information in your message: (1) name, (2) position title, (3) university afiliation, (4) specific description of your project of interest, and (5) your particular collaboration inquiry. Project A: CoherenceBackgroundCoherence protocols are one of the most challenging areas in computing and communication architectures. While the concept of sharing is not fundamentally difficult, the performance requirements of many computing systems requires aggressive coherence implementation techniques to make the performance penalties of coherence as low as possible. This has been a very active area of research and development in companies, labs and universities for many years, albeit mostly at the box and board level. As OCP is a point-to-point protocol, it is not within our scope to define the specific system, interconnect, nor protocols used to implement coherence. Rather, it is our intent to abstract such details away from the IP core designer to the extent possible (and rational). This should result in the ability for various system and interconnect topologies, running different styles of coherence protocols, with highly variable numbers of interacting devices, to be designed using OCP-compliant cores. Even at the point-to-point level, however, there is a fair amount of complexity in the underlying protocols. The user community would likely feel much safer in applying these protocols given defensible validation of the lowest-level protocols. Furthermore, it is clearly in OCP-IP's interest, and in the interest of OCP-IP's members, that implementation examples exist that show how existing styles of system-level coherence approaches can map onto the OCP coherence extensions. Validating the OCP coherence extensions, both in an ideal or formal sense as well as in reference systems, is a significant body of work. It is also work that we see as an ideal colloboration point between our industry organization and university researchers.
There is quite a bit of academic activity exploring the capabilities of single chips that integrate multiple processors. Some researchers are investigating systems where the processors have hardware coherence support. We suggest soliciting computing systems researchers and implementors working in such areas to consider implementing the OCP coherence protocols in their work. Ideally, such teams would build reference systems that implement these protocols, either in simulation, emulation, or actual chip designs. The availability of intermediate deliverables, both papers and executable models, is of great value to the OCP-IP community in exploring the scope and capability of the coherence extensions. We are encouraging researchers to consider taking common system-level coherence protocols into the on-chip domain, including:
There is ample investigative work implicit in this proposal to occupy four or five separate university teams for several quarters. We are confident that the various groups would ultimately enjoy ample opportunity to publish results without significant risk of collision. OCP-IP will assign a "sponsor" from the Specification WG to provide both coaching to the researchers and provide a conduit for their feedback into the specification process. Summary OCP-IP is offering this compelling value proposition for universities doing research into multi-processor embedded systems, and that this is the most probable course that OCP-IP could take to further validate our OCP coherence extensions. Project B: SystemVerilog TransactionsOCP-IP is eager to engage a university in collaboration in the area of SystemVerilog transactions. The System-Level Design WG has already completed a significant body of work in the area of SystemC transaction-level modeling, and is committed to a program of work along these lines with OSCI, a companion commercial trade organization. The WG is particularly interested in extending its collaborations to embrace SystemVerilog transactions. Rather than define a specific project, we encourage people to contact us directly with suggestions and proposals.Please contact research@ocpip.org for more information about potential collaboration in this area. |
