NoC Benchmarking Working Group: Early in 2006, the Governing Steering Committee ("GSC") of OCP-IP commissioned the activity of a working group to look at the area of Network-on-Chip ("NoC") Benchmarking. It has long been apparent that the preferred SoC design-style of "block-based design" would lead to an inevitable evolution in the manner in which these blocks (or IP-cores) would be connected. Not surprisingly, design-styles are evolving from deploying interconnect comprised of "dumb busses" to those featuring more intelligence and so ensure efficient data-management and Quality of Service (QoS), etc., very much in the way of traditional computer and other "system-level" networks.
The SoC design industry has long been familiar with such activity as benchmarking the performance of individual embedded processors. However, in a time where it is common for complex SoC's to feature a number of processor types (traditional embedded micros, DSP's, Media processors, Graphics processors and more) it is necessary for us to look more comprehensively and realistically at the performance of the ENTIRE system. These heterogeneous, multi-core processing systems are best evaluated under the umbrella of "NoC benchmarking." OCP-IP has brought together leading experts in this emerging field to develop schemes for evaluation of NoC performance that will ultimately help the SoC design industry and our members select and evaluate such commercial products as they become increasingly more commonplace.
Much of the work on NoC's has previously resided in universities and only recently have a few related commercial products emerged. Because of the completeness of the OCP specification and commercial demand, these supplier companies are members of OCP-IP. The work of the NoC Benchmarking Working Group ("NoC BWG") is centered on the expertise of leading universities operating in this area.
BWG produced a ground-breaking document describing the situation and
opportunities and making recommendations about the benchmarking of NoCs.
The white paper was developed by many of the leading experts in the
academic community and was reviewed by corresponding industry experts
within OCP before being published in February 2007. The white paper is available for free on our
In 2008, the NoC BWG announced the release of Parts 1 and 2 of their OCP NoC Benchmarking Specification. Part 1 details requirements and features for application programs, synthetic micro-benchmarks and abstract benchmark applications. It also discusses ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. Part 2 presents a generic NoC architecture, a comprehensive set of synthetic workloads as micro-benchmarks, workload scenarios and evaluation criteria. These micro-benchmarks enable you to pinpoint particular properties of NoC architectures complementing application benchmarks. Both parts of the NoC Benchmarking Specification are available here.
In 2010, the NoC BWG released the Transaction Generator (TG) package publicly. The TG is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multiprocessor system-on-chip (SoC) applications. Utilizing this tool makes simulation of larger systems substantially faster and the results obtained at this higher level can be accurately used as an initial estimate in selecting and fine-tuning NoCs.
The TG generates traffic for network-on-chip according to abstract software and hardware models. During simulation the TG measures performance metrics from the application and platform models, and from the traffic routed through network-on-chip. Because this freely available, highly-versatile tool, works on the transaction level, simulation of larger systems is substantially faster than those done at the clock-cycle accurate level.
The tool is freely available to both OCP-IP members and non-members alike through GNU LGPL, and is useful for all system-level designers evaluating various interconnection solutions in a simulation model of a real, complex system. It can also be used to simulate IP blocks before real implementations are available which enables the design of interconnect and implementation of IP blocks and SW for processors to advance in parallel, saving time, resources, and ensuring a faster time-to-market.
For a list of TG FAQs click here
The status and activities of the NoC BWG are featured in each edition of our quarterly Newsletter. If you wish to be involved with the NoC BWG or have questions regarding their activity, please contact us at email@example.com.
University Members: OCP-IP offers a University class of Membership. This provides an extremely low cost method for academic institutions and research bodies to receive all the benefits of membership at affordable rates. The membership is designed to provide essentially all the benefits of Community Membership, with the single exception that there is a limit on the amount of free technical support that will be provided. Applications can be completed in a matter of minutes by providing details on the Membership Application. More details and benefits of this membership class are provided in our University datasheet.
Many universities have chosen to use the OCP specification for both undergraduate and postgraduate work. In addition to those universities holding formal membership in OCP-IP, there are some 1,000 other universities and institutions around the world that have taken research copies of the OCP specification to support their studies and investigations. Our formal University Members include some of the foremost and most prominent academic and research institutions from around the world; these are listed alongside commercial members and partners within our corporate presentation, which can be found at here.
University members have found that the free training materials, verification software and extensive other deliverables (OCP-IP provides these free to members) are of great value in training, while also providing a foundation for advanced research in electronic design (particularly in SoC's, but also in FPGA's and other implementation styles). If you have questions regarding University Membership, please contact us at firstname.lastname@example.org.
A University section is regularly featured in our quarterly Newsletter, which is available free from the public side of our website at www.ocpip.org.
Bibliography: The OCP-IP website contains a very popular Bibliography that provides an exceptional resource for researchers from both academic and industrial backgrounds. The listing was created to identify landmark publications in the electronic design space, heavily flavored with SoC design content. As the Bibliography is provided in a public area of our website it is open to all visitors and can be viewed at here.
Since its inception, the Bibliography has been a very popular landing spot on our website. It is supported and regularly updated through the generous efforts of the Tampere University of Technology, Finland, who is one of our member universities. As we are diligently searching for important publications, should you have any suggestions for listings in the Bibliography, they should be sent for consideration to email@example.com.
The University of Tampere is very well-known in the academic community for research into electronic design and is particularly noted for its prominence in Network-on-Chip (NoC). We will be glad to forward your messages to our own contacts; please direct such inquiries to firstname.lastname@example.org.
University Datasheet: OCP-IP supports a University Membership. This low-cost membership offers participants all the essential benefits of regular Community Membership. It is designed to empower academic and research institutions with access to the OCP specification and the same entire surrounding set of deliverables and access, made available to industry members.
Our University Membership is broadly used for both undergraduate and postgraduate training and research, and benefits from the free training programs, verification tools and numerous utilities tools and specifications surrounding the OCP. The OCP standard itself is of course the essential anchor to much research work in advanced electronic design and development.