Videos from Accellera Day at DVCon U.S. 2021

DVCon US 2021Accellera Day is a day focused on standards development and technologies that you can apply immediately and those that will help to shape future activity. Accellera Day at DVCon U.S. 2021 was held virtually on Monday, March 1. consisted of a tutorial, five short workshops, and a UVM Birds of a Feather presented by Accellera working groups.

In case you were not able to attend or you would like to view the activities again, we've provided the videos below.


Tutorial: Portable Stimulus: What's Coming in 2.0 and What it Means For You

The Portable Test and Stimulus Standard (PSS) from Accellera lets you create a single representation of stimulus and test scenarios that are usable by a variety of users across different platforms and different integration levels throughout a verification project. This tutorial will share some of the important new features coming in v2.0 that were added to enhance the usability, programmability and portability of PSS. Presented by members of Accellera’s Portable Stimulus Working Group


Workshop: UVM-AMS: A UVM-Based Analog Verification Standard

Members of the UVM-AMS Working Group will share the work done so far in developing a comprehensive and unified analog/mixed-signal verification methodology based on UVM to improve analog mixed signal and digital mixed signal verification of integrated circuits and systems.


Workshop: UVM-SystemC Randomization - Updates From The SystemC Verification Working Group

Presented by members of the SystemC Verification Working Group, this workshop introduces the basic concepts of UVM-SystemC and shows how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the working group is working on the standardization of a common randomization layer based on CRAVE, a C++ and SystemC constraint randomization library. The workshop will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments.


Workshop: Getting to Know Accellera’s Emerging Hardware Security Standard: Security Annotation for Electronic Design Integration

Presented by members of the IP Security Assurance Working Group, this workshop introduces an emerging new standard called Security Annotation for Electronic Design Integration (SA-EDI) to address security concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to provide information about the IP security relevant to the integrator and recommended mitigations to implement and risk to address. At the conclusion of the workshop, viewers will better understand risks associated with IP and become familiar with the SA-EDI standard, including how it can be applied and when it will be available for reference.


Workshop: An Introduction to the Accellera Functional Safety Working Group Standardization Effort

This workshop is presented by members of the Functional Safety Working Group. This group of functional safety practitioners and experts from the industry are developing a standard that will provide a standardization definition of the Functional Safety data exchange to improve automation, interoperability, and traceability of the implementation of the Functional Safety guidelines and best practices during the lifecycle. The group intends the standard to capture a data model, language, or format to exchange data seamlessly among functional safety work products and across layers of the supply chain. This workshop presents some of the challenges in the industry for managing the exchange of data related to functional safety and then the goals and mission of the Accellera Functional Safety Working Group towards a new standard to address those challenges.


Workshop: Multi-Language Verification Framework Standardization and Demo

In this workshop, members of the Multi-Language Verification Working Group (MLVWG) present the current status of a proof-of-concept implementation and demonstrates its capabilities. A multi-language example is presented, which combines the UVM library in SystemVerilog and SystemC. Based on this example, the multi-language verification framework, its foundation concepts and the API targeted for standardization is explained and discussed. In addition, multi-language-specific UVM standardization requirements will be presented and language extensions will be proposed to address seamless integration and interoperability between UVM verification frameworks in SystemVerilog and SystemC.


UVM Birds of a Feather

The Accellera UVM Working Group has recently delivered a UVM library to match the IEEE 1800.2-2020 specification and is now considering which enhancements and bug fixes to work on next that would most benefit the user community. A complication is that many in the user community are still using older versions of UVM and so would not benefit from improvements to the 1800.2-2020 library. At a Birds of a Feather session at DVCon U.S. 2021, the working group gathered feedback from the user community through polling and a live Q&A to understand what could be done to help users get to 1800.2-2020 as well as what types of improvements would be the most useful.

In the presentation, members of the working group go through a brief history of UVM development in order to understand how they ended up with various versions that are not 100% compatible with each other.  They present the ideas that the working group is considering to expedite migration to the latest version and the ideas for future enhancements. 


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