Media Coverage

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2020

March 26th Standard Evolution
Semiconductor Engineering
March 26th Do You Trust Your IP Supplier?
Semiconductor Engineering
March 20th Create Once and Test Everywhere: The Promise of Portable Stimulus
Design News

2019

December 30th Silicon IP Security Proposal
EEJournal
November 13th Functional Safety Comes to EDA and IP
SemiWiki
November 1st Plotting a Course to Functional Safety
Amelia's Weekly Fish Fry
October 10th Accellera IP Security Standard: A Start
SemiWiki
September 13th DVCon U.S. Serves Chip Users Latest Tools and Standards
Semiconductor Digest
August 19th How Do We Tackle Chip Security?
EEJournal
July 22nd DVCon U.S. Serves Chip Users Latest Tools and Standards
ChipEstimate
June 25th Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 2 of 2)
Cadence Functional Verification Blogs
June 24th Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1 of 2)
Cadence Functional Verification Blogs
June 4th Accellera’s Chair Discusses Value of Membership
EDACafe
June 4th The Unknown Unknowns of Secure Devices
Tech Design Forum
June 4th DAC 2019: Day 1
Semiconductor Engineering
May 26th Semiconductor IP Security Issues
SemiWiki
March 19th Accellera Begins IP Security-Assurance Standards Effort
Tech Design Forum

2018

October 4th Accellera Tackles IP Security
SemiWiki
August 8th Agile Standards
Semiconductor Engineering
July 6th EDA Embraces Standard to Streamline IC Test and Verification
Electronics Weekly
July 2nd Tools Suppliers Back Version 1.0 of Portable Stimulus Standard
Tech Design Forum
February 1st DVCon US 2018 is Bigger and Better
EDACafe

2015

Summer 2015 Designing Efficiently for a Low Power World
EDACafe
March 5th DVCon: The Imitation Game
EDACafe
February 11th Accellera Systems Initiative Forms Portable Stimulus Working Group
Electronic Engineering Journal
February 11th Accellera Adds Portable Stimulus Group
Semiconductor Engineering