Community Newsletter: December 2018
IN THIS ISSUE:
- Message from the Chair
Much to be proud of in 2018, and a look forward to 2019
- DVCon U.S. 2019
New Chair looks forward to upcoming DVCon U.S.; the program is available and registration is open
- DVCon China 2019
DVCon China provides a valuable platform for IC design verification engineers in the region
- DVCon Europe Wrap-up
Record attendance at the 5th annual conference & exhibition
- SystemC Evolution Day Wrap-up
Full day workshop has more than 70 attendees
- Accellera Day India Wrap-up
Tutorials on UVM and Portable Stimulus well-received by attendees; DVCon India coming in September 2019
- Working Group Updates
SystemC Language Working Group Releases Version 2.3.3; SystemC Verification Working Group Releases 1.0beta2 Version; Portable Stimulus Working Group Releases Errata Document for PSS 1.0
- Accellera in the News
UVM 2017-1.0 is now available
As 2018 comes to a close, I look back over the year and I am very proud of the accomplishments and continued efforts of our Accellera working groups.
We began the year with new leadership in our Technical and Promotions Committees and have more involvement from our Board of Directors, giving even more members a voice.
Some things of particular note throughout the year include:
- The much anticipated Portable Test and Stimulus Standard 1.0 was announced at the Design Automation Conference in June.
- The Board of Directors approved the formation of the IP Security Assurance Working Group with great interest from the industry.
- A new addition to our family of conferences, Accellera Day India 2018 recently concluded with great fanfare and strong involvement from the local community. Our conference sponsorship began 30 years ago with the initial DVCon U.S., and our reach has grown to include DVCon Europe, recently celebrating its 5th year, DVCon China enjoying its 2nd successful year, and DVCon India (with Accellera Day India taking its 2018 slot).
- We are seeing a lot of interest in our new startup membership level, which has already resulted in new membership and participation in working groups.
Looking forward to next year, we eagerly await the release of UVM-SystemC 1.0 early in the year as well as an update to PSS 1.0. SystemC Synthesis will be updated with a 2.0 release, and the IP-XACT Working Group will begin a new round of updates commissioned by the IEEE 1685 Working Group. We are also looking forward to the return of DVCon India in 2019, marking six consecutive years of Accellera-sponsored conferences serving the design and verification community in India.
As always, we welcome and encourage membership participation in our working groups. The new IP Security Assurance Working Group is in its infancy and is quickly evolving. If this is an area of interest, please get involved in the development of this new and exciting standard. Our community pages are a good resource for information and I hope you will make use our forums to ask questions, make comments and give feedback as we continually strive to make improvements to our standards.
Lu Dai, Accellera Systems Initiative Chair
February 25-28, 2019
Message from DVCon U.S. General Chair Aparna Dey
Welcome to DVCon U.S. 2019! It is truly a privilege to present the DVCon conference and exhibition that will provide a tremendous opportunity for attendees to survey and learn the latest in Design and Verification technologies, methodologies and tools from the best in the industry.
Now in its 31st year, DVCon has established itself over the past three decades as the must-attend industry-focused conference for practicing design and verification engineers, EDA developers and design managers. Electronic designs and verification complexities and challenges continue to grow at a rapid pace, and we are very proud of our longstanding tradition of providing a very technical forum where colleagues can share practical knowledge and discuss challenges and solutions that can be beneficial in their current and upcoming projects.
With a record number of submissions, the 2019 conference promises to provide another outstanding technical program. We received nearly 160 excellent submissions for papers, panels, tutorials and short workshops from the best technical minds and organizations in the industry. The in-depth technical sessions and posters cover broad topic areas like formal verification techniques and methodologies, verification strategies, Portable Stimulus application and case studies, hybrid verification environments, UVM, power-aware design and verification, analog/mixed-signal verification, and more. Attendees will find each of these areas addressed at the conference’s sessions, panels, posters, tutorials and short workshops with an emphasis on real world solutions to engineers’ real world problems.
Our focus on the users of Accellera standard EDA languages, tools and methodologies continues to be a DVCon 2019 hallmark. Attendees can expect to learn about both practical solutions to their pressing problems and also receive a preview of the technologies that will affect them in the near future.
I sincerely look forward to seeing you in February in San Jose, CA at DVCon U.S. 2019!
DVCon U.S. 2019 General Chair
April 17, 2019
Message from DVCon China General Chair Bin Liu
I am honored to be the General Chair of the third annual DVCon China, and I look forward to participating in this conference with many of my IC industry friends. DVCon is an influential conference in IC design verification, and its expansion into China reflects the rapid development of the domestic IC industry over the years as well as the desire of IC practitioners to exchange engineering experiences among their peers.
DVCon China is providing such a valuable opportunity for IC design verification engineers across the country to learn the latest tools and ideas from the industry, to understand the design verification pain points of different companies in the face of increasingly complex chip systems, and to learn about other people's solutions to complex engineering problems. The gap between IC design and verification is widening as software is criticized for its hardware structure and design, which is not keeping up with software needs. To solve this problem, the EDA companies providing the methodology and tools to improve innovation must also consider how to build on the existing verification technology to make it more intelligent.
I look forward to seeing further developments and practical use cases for the Portable Stimulus Standard (PSS) at DVCon China as well as companies demonstrating interesting applications that combine AI data learning with verification-related databases. The DVCon China conference is positioned not only to enable attendees to understand the latest IC design verification technology applications, but also to enable IC design verification to become more professional at home. While improving the specialization of design verification, we also need to make efforts to alleviate the shortage of IC design verification talents.
I have been actively coordinating with universities to promote chip verification education, and this year my team and I will offer the IC Verification Foundation course through MOOC (an online class) to meet the needs of national students for chip verification education. I have reason to believe that the development of IC in China requires the technical exchange of ideas between engineers from different companies, the need to strengthen cooperation between enterprises and universities in the field of production, and the need for the EDA companies to interact more closely with the design companies. Quality of employment, personnel reserves and the production of tools to help in many ways will create a solid foundation for rapid development of IC design in China.
I would like to work with all attendees of the third DVCon China to contribute to this wonderful and great desire. I look forward to seeing you in Shanghai in April 2019!
DVCon China 2019 General Chair
DVCon Europe had a record number of attendees at the 5th annual conference held in Munich in October. Attendance at Europe’s premier design and verification conference grew by 20% with attendees representing 70 different companies from 27 countries. Drawn to the impressive technical program, which discussed notable new concepts across multiple areas, many in attendance were first-timers to DVCon Europe. The Exhibition was sold out with 22 exhibitors participating. Read the press release for a complete summary of the conference.
“This year’s DVCon Europe brought a great mixture of innovative topics to the design and verification community, including functional safety, virtual prototyping, machine learning, portable stimulus, RISC-V and much more,” noted Martin Barnasconi, DVCon Europe 2018 general chair. “I am pleased to see a growing interest in DVCon Europe participation throughout the engineering community as users share their experiences on the application of EDA standards, languages and methodologies for SoC design and verification.”
Save the Date! DVCon Europe 2019 will be held at the Holiday Inn in Munich, Germany on October 29th and 30th.
More than 70 attendees participated in the third SystemC Evolution Day. It was an informative, full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. For the first time, the workshop was co-located with DVCon Europe. In several in-depth sessions, select current and future standardization topics around SystemC were discussed in order to accelerate their progress for Accellera/IEEE standard’s inclusion. The presentations from SystemC Evolution Day 2018 are available for download.
SystemC Evolution Day 2019 will be co-located again with DVCon Europe and will be held on October 31st at the Holiday Inn in Munich, Germany.
Accellera Day India held a very successful full-day conference with close to 200 in attendance in Bangalore last month. Cliff Cummings provided tips & tricks for navigating UVM and the changes and features that are part of the new IEEE 1800.2 standard. Experts from the Portable Stimulus Working Group, Sharon Rosenberg and Pradeep Salla, provided updates on the new 1.0 standard, and Srini Maddali from Qualcomm provided an exciting keynote focused on the “Challenges in Validation of Low Power, High Performance and Complex SoCs at Optimal Cost.”
DVCon India 2019 will be held in September next year. Stay tuned for more details coming soon!
SystemC Language Working Group Releases Version 2.3.3
The Accellera SystemC Language Working Group (LWG) has released version 2.3.3 of the SystemC Class Library reference implementation. The LWG is responsible for the definition and development of the SystemC core language, the foundation on which all other SystemC libraries and functionality are built. This new version addresses approximately 40 issues reported by the user community and the working group members. A new convenience macro SC_NAMED has been added to the new release, simplifying the creation of named SystemC modules, objects and events. The features in the 2.3.x releases will serve as baseline for Accellera contributions to the restarting IEEE P1666 Working Group, working on the new revision of the SystemC standard. Version 2.3.3 has been released under the Apache 2.0 License and is now available for download.
SystemC Verification Working Group Releases 1.0beta2 Version
The Accellera SystemC Verification Working Group (VWG) has released the 1.0beta2 version of the UVM-SystemC reference implementation. This version incorporates fixes and improvements based on the public review period conducted earlier this year. Note that this UVM-SystemC reference implementation and language reference manual (LRM) is NOT considered final and approved. The main purpose of this implementation is to provide a proof-of-concept that the ideas embedded in the UVM-SystemC standard are achievable. Please check the frequently asked questions for more information about the UVM-SystemC functionality and capabilities. The UVM-SystemC reference implementation has been released under the Apache 2.0 license. The Verification Working Group welcomes your feedback. You can e-mail your feedback to email@example.com or contact us in the UVM-SystemC forum. We will make every effort to properly assess and incorporate feedback received in future releases of the LRM or reference implementation.
Portable Stimulus Working Group Releases Errata Document for PSS 1.0
The Portable Test and Stimulus 1.0 Errata document includes corrected examples and text clarifications to address issues present in the Portable Test and Stimulus 1.0 Standard. This document is meant to be read in conjunction with the 1.0 standard as it shows additional text in blue and deleted text as “strikethrough” text. There is no new functionality detailed in this document, only fixes and clarifications to existing functionality in the 1.0 standard. The Portable Test and Stimulus Standard 1.0 and Errata document are available for download.
Accellera’s Portable Stimulus community is a good resource for the latest information on the standard. The working group also encourages readers to ask questions and interact with the working group via Accellera’s Portable Stimulus forum.
UVM 2017-1.0 is Now Available!
The Accellera Universal Verification Methodology (UVM) Working Group has released the UVM 2017-1.0 reference implementation. UVM 2017-1.0 is aligned with the IEEE 1800.2 standard and the enhancements that make it more powerful and easier to use. UVM 2017-1.0 also includes full documentation of the API that is provided in addition to 1800.2-2017.
The UVM 2017-1.0 reference implementation can be downloaded for free from Accellera. The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. Visit the UVM forum to provide feedback, ask questions, and engage in discussions. For more information on UVM, visit the UVM community.
2018 Global Sponsors
Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.
Copyright 2018 Accellera Systems Initiative